Hello,

I'm using a Zync part (Xilinx Series-7) and trying to use the dynamic reconfiguration of the MMCM clock module whilst keeping the fine phase shift control enabled as I need both features.

The 'famous' application note XAPP888 gives an example but explicitly says that fine phase shift doesn't work with it. (I say famous because on the Xilinx forums regardless of the questions any official answer gets a reference to this application note in the response even if not really relevant!).

It doesn't say that using both features is impossible and searching the Xilinx forum shows a number of people who have needed to do the same thing. It seems they have succeeded but it isn't clear how.

Does anyone know specifically how to re-enable the fine phase shift control of the MMCM after performing a run-time reconfiguration? That would be very helpful information please!

Also I have suggested through my Xilinx FAE that this app note is updated to show fine phase shift support with DRP control as clearly a number of people need this functionality. Hopefully this will happen one day.

Regards

Paul

Paul (@paulkushner),

I do not have any direct experience trying to use an MMCM is such away, I don't have an answer to your specific questions.  But I am familiar with others that have went down similar paths trying to use an MMCM (or the prior DCM) with no success - that is trying to dynamically adjust the MMCM/DCM.  If Xilinx (or the famous app) implies it might not be a good idea, I would look for a different solution.

Regards,
Chris

Hi Chris,

Thanks for your reply.

Just to clarify I have both fine phase shift control and dynamic port reconfiguration working successfully in hardware but not together. As soon as an MMCM reconfiguration has been completed the phase shift control stops working. A user on the Xilinx forum has suggested that a register bit needs to be set but I cannot work out which one or how. The Xilinx datasheet itself is actually very helpful and the provided code works well. 

Paul

I have an answer from Xilinx, see the following link for the info on the Xilinx forum:

https://forums.xilinx.com/t5/7-Series-FPGAs/Can-we...

If anyone else wants to do this then tell Xilinx! They can't commit resource to updating the app note and support files until there is enough demand.

Regards

Paul

I have successfully used the DRP before to dynamically change the clock frequency, but haven't tried fine tuning the phase.