I want to design a UART receiver/transmitter and by now I already developed the receiver vhdl file but when declare and instantiate the the receiver component on my Mainboard Design I get very much syntax errors in both files, mainboard and uart-receiver.

The following is the mainboard design. I use generics. Could the problem be here? I already tried different approaches like setting the generics with ":" or with "=>" in the instantiation but nothing worked. It is a vhdl design for an altera FPGA (Cyclone V), I'm using Quartus II Lite. I got the design from an Internet Site (https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html)

LIBRARY IEEE; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;

ENTITY mainboard is PORT( CLOCK_50_B5B : IN STD_LOGIC;
        LEDG : OUT STD_LOGIC_VECTOR(7 downto 0);
        LEDR : OUT STD_LOGIC_VECTOR(7 downto 0);
        KEY : IN STD_LOGIC_VECTOR(4 downto 0);
        CPU_RESET_n : in STD_LOGIC;
        GPIO : INOUT STD_LOGIC_VECTOR(36 downto 0)
     ); END ENTITY;

ARCHITECTURE behavior of mainboard is SIGNAL LED_7 : STD_LOGIC; SIGNAL LED_6 : STD_LOGIC; SIGNAL CLK100 : STD_LOGIC; SIGNAL locked : STD_LOGIC; SIGNAL SF_D_signal : STD_LOGIC_VECTOR(3 downto 0); SIGNAL Reset : STD_LOGIC; SIGNAL RX_byte_sig : STD_LOGIC_VECTOR(7 downto 0);

component uart_rx
generic (g_CLKS_PER_BIT : integer); port (
  i_clk       : in  std_logic;
  i_rx_serial : in  std_logic;
  o_rx_dv     : out std_logic;
  o_rx_byte   : out std_logic_vector(7 downto 0)
  );
  end component;



component Test1_Led
port ( clk_in : in STD_LOGIC;
        led_out : out STD_LOGIC); end component;

component test
port ( refclk   : in  std_logic;
        rst      : in  std_logic;
        outclk_0 : out std_logic;        -- outclk0.clk
        locked   : out std_logic); end component;

component lcd_control
port ( clk : in STD_LOGIC;          
         reset : in STD_LOGIC;      
         init : in STD_LOGIC;
         init_ok : out STD_LOGIC;
         row_select : in STD_LOGIC;
         Data_in : in STD_LOGIC_VECTOR(19 downto 0);
         SF_D : out STD_LOGIC_VECTOR(11 downto 8);      
         LCD_E : out STD_LOGIC;     
         LCD_RS : out STD_LOGIC;    
         LCD_RW : out STD_LOGIC;    
         SF_CE0 : out STD_LOGIC);   
end component;

constant c_CLKS_PER_BIT : integer := 54;



BEGIN

lcd1 : lcd_control
port map ( clk => CLOCK_50_B5B,
              reset => Reset,
              init => '1',
              init_ok => LEDG(0),
              row_select => '0',
              LCD_RS => GPIO(35),
              LCD_RW => GPIO(33),
              LCD_E => GPIO(31),
              SF_D(11 downto 8) => SF_D_signal(3 downto 0),
              SF_CE0 => GPIO(0),
              Data_in => "00010010001101000000");

led1 : Test1_Led
port map ( clk_in => CLOCK_50_B5B,
              led_out => LED_7);

led2 : Test1_Led
port map ( clk_in => CLK100,
              led_out => LED_6);

test_inst : test
port map ( refclk => CLOCK_50_B5B,
              rst => not KEY(0),
              outclk_0 => CLK100,
              locked => locked);

uart_rx_inst : UART_RX
generic map ( g_CLKS_PER_BIT => 54) port map (i_Clk => CLOCK_50_B5B,
          i_RX_Serial => GPIO(1),
          o_RX_DV => LEDG(3),
          o_RX_Byte => RX_byte_sig);




Reset <= not CPU_RESET_n;                 

LEDG(7) <= LED_7;
LEDG(6) <= LED_6;
LEDG(5) <= CPU_RESET_n;
LEDG(4) <= Reset;

LEDR(7) <= GPIO(1);


GPIO(19) <= SF_D_signal(0);
GPIO(21) <= SF_D_signal(1);
GPIO(23) <= SF_D_signal(2);
GPIO(25) <= SF_D_signal(3);
LEDR(3 downto 0) <= SF_D_signal(3 downto 0);


END ARCHITECTURE;

The Uart Design File (entity) is coded like this:

library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.all;

entity UART_RX is
 generic (g_CLKS_PER_BIT : integer := 54);
 port ( i_Clk       : in  std_logic;
       i_RX_Serial : in  std_logic;
       o_RX_DV     : out std_logic;
       o_RX_Byte   : out std_logic_vector(7 downto 0)); end UART_RX; ...

I got the following errors:

    Error (10500): VHDL syntax error at mainboard.vhd(96) near text "Â"; expecting >";", or "port", or "generic"

    Error (10500): VHDL syntax error at mainboard.vhd(97) near text "port"; >expecting "<="

    Error (10500): VHDL syntax error at mainboard.vhd(98) near text "Â"; expecting >"!", or "=>"

    Error (10500): VHDL syntax error at mainboard.vhd(99) near text "Â"; expecting >"!", or "=>"

    Error (10437): VHDL Association List error at mainboard.vhd(98): positional >associations must be listed before named associations

    Error (10500): VHDL syntax error at mainboard.vhd(100) near text ";"; >expecting "<="

And in uart file:

    Error (10500): VHDL syntax error at UART_RX.vhd(5) near text "Â"; expecting >"entity", or "architecture", or "use", or "library", or "package", or >"configuration"

    Error (10500): VHDL syntax error at UART_RX.vhd(7) near text "Â"; expecting >"end", or "begin", or a declaration statement Error (10523): Ignored construct UART_RX at UART_RX.vhd(6) due to previous >errors

    Error (10500): VHDL syntax error at UART_RX.vhd(15) near text "Â"; expecting >"entity", or "architecture", or "use", or "library", or "package", or >"configuration"

    Error (10500): VHDL syntax error at UART_RX.vhd(18) near text "Â"; expecting >"begin", or a declaration statement

    Error (10500): VHDL syntax error at UART_RX.vhd(20) near text "Â"; expecting >")", or "," Error (10500): VHDL syntax error at UART_RX.vhd(21) near text "Â"; expecting >"begin", or a declaration statement

Can you help me finding the mistake?

Hi Jamanen,

  Perhaps this example code at  https://opencores.org/project,simple_uart_for_fpga  can help. It is a UART that I have compiled successfully onto a Cyclone V FPGA. It also uses generics to declare clock frequency, baud rate and parity. 

Hi!Thanks for your help. I'll take the code for reference.It really helps!