Aurora 8B10B for Virtex-4 FX FPGA Generation Failed Using ISE 14.7

Started by Multan007 1 year ago2 replieslatest reply 1 year ago52 views

I am trying to generate the Aurora 8B10B core for Virtex-4 FPGA using ISE 14.7 in Windows 7  (64 bit) OS based on the procedure presented in LogiCore IP guide. But, after running 18% of core generation, I see:

WARNING:coreutil - WARNING: EJava Unzip Failure on for ./\\aurora_interface\ Zip/Jar file, C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\network\com\xilinx\ip\v4fx_aurora_8b10b_v3_1\, is not a valid file.

WARNING:sim:93 - NGC output will not be generated for this core.

Finished Generation.

Generating IP instantiation template...

Finished generating IP instantiation template.

Generating ASY schematic symbol...

Initializing IP model...

Finished initializing IP model.

ERROR:sim - c_mgt_clock_1: Invalid value 'None'.

ERROR:sim - Failed to generate ASY schematic symbol.

Could you please advice the cause and possible solution for this warning and error?

I appreciate your suggestions. Thanks for your answer and time

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Reply by rajkeerthy18April 3, 2018

I was told by a Avnet support engineer that ISE 14.7 works best on Windows 7 32 bit. I had similar issues with later versions of ISE 14.7 and switched to WIndows7 32 bit, works fine, I got a 10 year old laptop  repaired for this. It was worth it.

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Reply by Multan007April 5, 2018

Thanks for your kind response. But, unfortunately we do not have 32 bit right now. However, I will try manage 32 bit and run the test again. Hope, you suggestion will work!