I am trying to generate the Aurora 8B10B core for Virtex-4 FPGA using ISE 14.7 in Windows 7 (64 bit) OS based on the procedure presented in LogiCore IP guide. But, after running 18% of core generation, I see:
WARNING:coreutil - WARNING: EJava Unzip Failure on fileset.zip for ./\\aurora_interface\_tmpjava.util.zip.ZipException: Zip/Jar file, C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\network\com\xilinx\ip\v4fx_aurora_8b10b_v3_1\fileset.zip, is not a valid file.
WARNING:sim:93 - NGC output will not be generated for this core.
Generating IP instantiation template...
Finished generating IP instantiation template.
Generating ASY schematic symbol...
Initializing IP model...
Finished initializing IP model.
ERROR:sim - c_mgt_clock_1: Invalid value 'None'.
ERROR:sim - Failed to generate ASY schematic symbol.
Could you please advice the cause and possible solution for this warning and error?
I appreciate your suggestions. Thanks for your answer and time
I was told by a Avnet support engineer that ISE 14.7 works best on Windows 7 32 bit. I had similar issues with later versions of ISE 14.7 and switched to WIndows7 32 bit, works fine, I got a 10 year old laptop repaired for this. It was worth it.
Thanks for your kind response. But, unfortunately we do not have 32 bit right now. However, I will try manage 32 bit and run the test again. Hope, you suggestion will work!