Hi, 

So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently, for my project I have upgraded the clock cycle of the FPGA to 150 MHz. The reason I want to do this is:

I am using Mojo board for coincidence counting experiments and I am feeding signals (generated by signal generator) from two channels onto the mojo, which is then connected to a computer with a GUI designed to display counts.The problem is if I set the frequency of the signal in a channel to be 10 MHz, let's say, I am losing about 110 counts. So, I think it might be because there is no synchronization in the clock cycles of the FPGA and the generator.

Any resources on how to do this? Has anyone tried this before?

Hello,

just my two cents: what about doing the opposite?  Most function generators accept an external clock reference (often, at 10MHz).  In my opinion it would be much easier to have the FPGA generate the required reference and feed the generator rather than the opposite.

Regards,
Ivan

Yes, that is exactly what I am trying to do. Generate a 10 MHz clock from the FPGA and then supply it as an input to the function generator. Any reference on how to do that?

Please take this with a grain of salt because I'm not an expert on the Spartan.  I did in on the Zynq though.  You can use the DCM to generate a clock at the frequency you wish and route it to an output pin.

http://www.xilinx.com/support/documentation/user_g...

Beware that these PLLs can be jittery and the output may be affected by switching noise.

Thank you for the reply. I used coregen to create a 10 MHz clock signal from the FPGA. Is there any documentation on how to take that signal out of the FPGA and allocate a certain pin through which I can take that signal as an output?