## A Law compression for FPGA

Started by 6 years ago7 replieslatest reply 6 years ago258 views

Hi all,

Referring to this doc on A law compression (table 1):

http://www.young-engineering.com/docs/YoungEnginee...

The table is meant for 13 bits signed to 8 bits signed.

In my case I have to compress 16 bits to 8 bits and when I apply the above table I get the positive range correct but the negative range reduced by half  or so. Can anybody help explain how to implement the compression using such table or what could be missing.

Thanks

Kaz

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Hi Kaz,

Did you use exactly that table to compress the 15 bits + sign into 7 bits + sign? Or did you make a new table?

Can we see the code?

Regards,

Josy

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Hi Josy,

Thanks for the reply. I haven't access to code right now but I shifted the 13 bits table towards MSB then kept the same pattern. for example the lowest table entry of "1,A,B,C,D,xxx...] was moved to bit index 14 for '1' and bit index 13:10 for ABCD

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Kaz,

Thus effectively discarding the 3 lowest bits of the input data?

Did you convert the 2's complement into sign + (unsigned) magnitude, before discarding the 3 lowest bits?

Regards,

Josy

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I did first convert negative values to unsigned(though that is not stated in the doc) then all negative values were opposite in trend. So I removed the conversion and now for the range +32767 to -32768 I get +127 to -80 !! but correct in trend.

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convert to unsigned as in:

def twos2sm( a ):

''' accept a 16 bit signed input vector and

return the sign and magnitude '''

if a[15]:

# negative

return 1, 2**15 - a[15:0]

else:

return 0, a[15:0]

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