What would be difference between clock latency and propagation delay?

Started by tip_can19 3 months ago4 replieslatest reply 3 months ago88 views

I believe the clock latency is the total time it takes from the clock source to an end point.

latency_60152.png

Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below.

propagation_46121.png

So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture?

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Reply by matthewbarrOctober 25, 2018
I think you have this right, exact terminology may vary depending on what you're reading or who you're talking to. What is called clock latency in the first diagram is the clock signal propagation delay through the clock tree from the clock source (PLL) to a register clock input. In this case all clock paths are non-inverting so you're looking at rising edge to rising edge propagation delay. The difference in clock latency from source to two different register clock inputs is the clock skew between those two inputs. Clock skew can be your enemy because it can create difficult register-to-register data hold time situations, and can be your friend because it spreads out the register clock events thus reducing the magnitude of the current spike associated with clocking a large number of registers at the same time. Another common use of the term latency in the context of a clock signal is the number of clock cycles it takes for something to happen. For example, when you make a read data request to a hierarchical memory system there will be some number of clock ticks before the data is returned. This is commonly called memory latency, you'll have a minimal latency if the data is found in level 1 cache, longer if found in level 2 cache, etc.

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Reply by tip_can19October 28, 2018

Thank you very much for the detailed explanation!


Regards

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Reply by CustomSargeOctober 25, 2018

Signal timing pends who needs to get what at the same time (synchronous signals) as versed to event triggering sequences (asynchronous signals).

You can have both in your system design, by being careful to know the sync sections are ok with the async sections. F/Fs are real handy at being semiphores as to data syncing.

It Will test your design acumen, but also be a learning point.

A well designed multiprocessor environment is choreography in action. Not easy to do, but rewarding to pursue and succeed. BTDT Fun Stuff...   <<<)))

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Reply by tip_can19October 28, 2018

Thank you!