I believe the clock latency is the total time it takes from the clock source to an end point.
Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below.
So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture?
Thank you very much for the detailed explanation!
Signal timing pends who needs to get what at the same time (synchronous signals) as versed to event triggering sequences (asynchronous signals).
You can have both in your system design, by being careful to know the sync sections are ok with the async sections. F/Fs are real handy at being semiphores as to data syncing.
It Will test your design acumen, but also be a learning point.
A well designed multiprocessor environment is choreography in action. Not easy to do, but rewarding to pursue and succeed. BTDT Fun Stuff... <<<)))