Recommended references for writing a DSP IP core using Verilog.

Started by StefanOrosco 3 years ago2 replieslatest reply 3 years ago347 views

Hey all,

**I am new to this forum so if this is not the correct format or information location then please let me know**

I am working with an RF daughter card from Analog Devices and a Zedboard as my main processing system. I have the most recent copy of Vivado 2018.3. I am trying to find reference material for implementing DSP IP cores in verilog, currently I am attempting to achieve Binary Phase Shift Keying, however, I have hit a wall in that I am finding that much of what I don't know is on the FPGA side. Like the actual building of the IP core and clocking etc. I am fairly good at the DSP portion and I know what I need to do, but I just need figure out how to wrap that in a hardware core. I really would like the advice of those who work with verilog and perhaps Vivado. 

What books/reference material did you work with to get where you are now? 

Any recommendation would be appreciated! 

I have the Zynq book and can create basic IP cores and Block Diagrams to control the hardware, but I am looking for a way to boost myself from the beginer level to the intermediete level.  

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Reply by rajkeerthy18January 20, 2019

Any recommendation could get too long for a forum discussion. However an itemized recommendation to get a start is possible.

1. If you are new to Verilog, you would have to learn hardware design using Verilog.    2. If you already know the DSP algorithms you have to think how to implement in Verilog, you may first write the algorithm in C and then translate it to Verilog.                 3. If you have MATLAB tool you could do the system design using MATLAB and then get a Verilog code from HDL coder. Xilinx has a Sysgen tool please checkout.                    4. After all this, you would have to get handy with VIvado.                             5. From step 2, you could use HLS tool and generate FPGA bitstream.

These steps are easy to suggest but learning curve is deep. After that curve there would be a new world. Good Luck.

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Reply by jclelannJanuary 22, 2019

I suggest having a look at Pr Pong Chu series about FPGA Prototyping.