I'm trying to generate True Two port RAM module in Clarity Designer in Lattice Diamond.
Lattice Diamont is 3.10 .3.144, 64 bits, with SP3 installed.
Project is for ECP5.
I try to generate this, i think, the only possible way:
The only changes I made is change Verilog to VHDL, and set proper address and bit width settings.
But in the final window, when i click "Close", i have Error:
Why? There are something to do i missed?
Thank you in advance.