Mixed columns for AES algorithm

Started by Lynam 3 years ago1 replylatest reply 3 years ago31 views

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Reply by rajkeerthy18March 21, 2019

A much simpler alternative could be that your new algorithm be developed in C/C++ and validated in a C/C++ suite. Later the same could be ported to FPGA using the HLS methodology. Xilinx provides vivado tool HLS edition. Ofcourse you have to learn HLS, it is not difficult though. This is much faster though and fits your true goal which is to develop an algorithm. The HDL method would require that you learn the HDL, simulate, debug and then target FPGA which is a longer route. Simulation in C/C++ is much much faster compared to HDL simulations.