Hi.

I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip.

FT601Q have 32-bit input/output port. To achieve full throughput, all of this 32 bits should be used.

But the TXE_N signal indicates one byte free space in FIFO, not four (from "3.2 Device Pin Out Signal Description"):
"TXE_N: 245 Synchronous FIFO mode: Transmit FIFO Empty output signal. The signal indicates there is a minimum of 1 byte of space available to write to. Only write to the FIFO when this signal is logic 0.
So it looks like that only 8-bit input is correct to manage FIFO. Wider input, witch only 1-byte TXE_N indication, could cause overflow the FIFO.
Is it even possible to achieve transmit without losing some of data, in this mode and 32-input?
I misunderstand something, or it is another error in the structure of FT601Q, not described in the FT601Q errata?

If the data sheet says minimum 1 byte writable, 32 bits would be reduced to 8 bits. You may have to get clarification from the vendor if it is 1 byte or 1 dword.