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SPI core in EDK generates junk output

Started by shreeranjani 1 month ago22 views
Hi ,

I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave).
Microblaze is operated at 50Mhz input clock. spi in edk is configured as:
1) MISO => input
2) MOSI => output
3) SCK => output
4) SS => output.

My simulation is not as per elf file generated from SDK. My spi signals in edk is not reflected on top module of ise all are uninitialized.


i would appreciate for your response.

Can anyone please direct me how I can start doing it ? Is there an example ?

With regards,
Shreeranjani