How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?
I try to use "PROHIBIT PRIMARY" preference, as described in:
TN1263 ECP5 and ECP5-5G sysCLOCK PLLDLL Design and Usage Guide.pdf

But this cause an error:ERROR - Pin driven clock 'CLK_IN_FROM_IO_c' cannot use general routing if PROHIBIT PRIMARY statement is used. PROHIBIT can only be used for gated (slice) driven clock.

I don't use GROUP preference, because I quess it is used only to optimizing the signal path. Not for enable to use non-dedicated IO as clock input.I cannot use dedicated IO pin because it is prototype PCB and it has same mistakes.