Timing paths from wires to registers

Started by kaz 1 year ago3 replieslatest reply 1 year ago36 views

Hi All,

I 've come across this case (please see figure below) .

I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them is selected by a mux (combinatorial) per system clock without any register between them and the multiplier result register. The path indicated by the dotted line could suffer unknown delay and skew yet I don't think a timing tool will check it.

To my understanding a timing tool (synopsis based) will not recognize it as timing path since the path definition is that between two registers and this one is not.

I know I can put registers on the constants A,B,C,D but might not.... 

isn't this a potential pitfall? Any thoughts please.



timing path question_91908.jpg

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Reply by rajkeerthy18November 7, 2019

There are timing paths from 2 sides, the input to output and constants to output, and up to D input of the final register is a combo block. The source of multiplicand and constants has to be specified for timing analysis and the tool handles it correctly.

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Reply by kazNovember 9, 2019

I have already indicated those timing paths. What I am questioning is the behavior of the tool itself. Vivado timing does not report warning of unconstrained paths on those I mentioned.

I know tools warn of unconstrained paths from io for example but shouldn't they report unconstrained paths from wires(constants) as well. That is my issue.

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Reply by rajkeerthy18November 10, 2019

STA does consider arrival time and wired delay of signal inputs. In this case arrival time is 0 and these are not primary inputs. Only wire delay is considered for STA. That could be the reason for the tool not to report the path as unconstrained. This may not fully answer the question. You could post this question in Xilinx/Synopsys forum also and see what is the response.