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DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 1 year ago5 replieslatest reply 1 year ago81 views

I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the drivers, I have no sources as to how I can actually program the thing. Has anyone here had success with the DPL who can help me with the Pin Planner? The FPGA on board is an Altera(Intel) Cyclone IV EP4CE6E22C8N. I have searched the internet extensively and found NOTHING on this board.

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Reply by prashantpdNovember 29, 2019

The DueProLogic website has a sample projects zip https://www.earthpeopletechnology.com/products-pag...

Inside the sample project zip file you will find the following platform demo project 

DUEPROLOGIC_USB_FPGA_PROJECT_2.8_DVD\Projects_HDL\EPT_4CE6_AF_Platform_Demo\EPT_4CE6_AF_Platform_Demo\EPT_4CE6_AF_D1_Top that has a qsf file which lists the pin assignment. You should be able to use it as a starting point. Any other pins not assigned in the sample project may be identified in the schematic.

There is also a Tutorial.pdf in the zip file that you may refer to.


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Reply by AwesomeCronkNovember 29, 2019

I have tried that manual before. That pdf is so out of date it hurts. Most of the files it talks about don’t exist anymore. Thank you for finding that pin file. I will look at that and try to pick it apart

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Reply by AwesomeCronkDecember 6, 2019

After trying that, I got the zip, opened the .qsf, and found references to other files in the project. I just want to know how to declare pins.

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Reply by prashantpdDecember 6, 2019

Good you found the qsf

If you open the file at DUEPROLOGIC_USB_FPGA_PROJECT_2.8_DVD\Projects_HDL\EPT_4CE6_AF_Platform_Demo\EPT_4CE6_AF_Platform_Demo\EPT_4CE6_AF_D1_Top\EPT_4CE6_AF_D1_Top.qsf, you will see that it has the following lines

...

set_location_assignment PIN_11 -to bc_in[1]
set_location_assignment PIN_10 -to bc_in[0]
set_location_assignment PIN_3 -to bc_out[2]

...

This corresponds to the location assignment of the port bc_in[1:0] and bc_out[2] to the pins PIN_11, PIN_10 and PIN_3 as shown in the schematic


The schematic naming and port naming does not match exactly, but I guess the name in the qsf will match with the port name in the top level source file.


You can try building the sample project and see if the assigned pins throw up any errors

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Reply by AwesomeCronkDecember 6, 2019

So, I am going to avoid the sample project. I presume I can make a block diagram (.bdf, I think) and use those lines in a custom .qsf file. I will try that tomorrow (?) or next day