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Andrew Isaak (@Duhast)

Work with FPGA as R&D engineer.

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 5 years ago (04/15/2019)
Every registers  and memory of your scheme should be clock by one signal, ‘clk’ in your case. Search for ‘synchronous design’.To get a certain element ...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 5 years ago (04/14/2019)
Hi. You have a declaration in your code: reg clock; The width of clock here is 1. But later you use it as a counter with range 0 to 100:clock <= clock + 1;     if(clock...

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