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Sheshu Ramanandan (@Knight123)

FPGA Design Engineer

Re: How to avoid Blocking Statement in Verilog

Reply posted 4 years ago (05/31/2020)
I think this could be one way.always@(posedge clk)begin    if(carr_phase_s + delt >= 26)      carr_phase_s <= (carr_phase_s + delt) -26;    else     ...

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