Michael Kellett (@MichaelKellett)


Re: Will this FPGA be suitable for DSP purposes?

Reply posted 3 years ago (10/05/2020)
Assuming that your maximum signal frequency will be 200kHz and the sample rate around 1Mhz the Artix 35 FPGA is perfectly capable of realising some kind of digitally...

Re: Does anyone have experience in RFSoCs?

Reply posted 3 years ago (05/09/2020)
Crumbs ! I feel your pain !How long have you got for this - Xilinx have been busy trying to get people to believe that you just click a few bits of pre-baked code...
You will almost certainly need buffer memory outside the FPGA. If you design the system to operate at close to or over 1GB/s you are setting yourself to fail. Start...
Assuming that the data source and PC have no more than one (maybe 2) switch(es) between them UDP is the way to go. You will need to design your own protocol to cope...

Re: Use of DAC in ZCU111 Dev Board

Reply posted 4 years ago (08/14/2019)
I don't have any application for the RFSoc parts so no useful help to offer. (Hence the apology at the start of my post :-)For what it's worth I usually start of...

Re: Use of DAC in ZCU111 Dev Board

Reply posted 4 years ago (08/14/2019)
Sorry, can't resist asking - what sort of square waves do you need that you are using an $8k+ dev board to generate them ?MK

Re: FPGA curve fitting

Reply posted 6 years ago (09/10/2017)
Sorry, I can't help you because you either can't or won't provide the level of information needed. So far you've told us that you have an unknown 12 bit ADC and...

Re: FPGA curve fitting

Reply posted 6 years ago (09/06/2017)
This may sound a bit rude but you are not going about asking this in a sensible way.If you already have some parts then tell us exactly what they are - which ADC...

Re: Mealy or Moore? none and not even state machine

Reply posted 7 years ago (10/13/2016)
The name thing shouldn't be too hard really - just don't be too pedantic about it. I might have states with names like:INIT, READ, WAIT_FOR_SIGNAL but if read wants...

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