25+ Years experience in embedded electronics, FPGA and firmware development.

Re: Lattice MachXO2 Timing errors.

Reply posted 2 years ago (09/02/2019)
Thanks for those exceleent suggestions! I'll give it a try.

Re: Lattice MachXO2 Timing errors.

Reply posted 2 years ago (08/30/2019)
Thanks for the reply! Much appreciated.I will look carefully at your suggestions - thank you!Some more info: The MachXO2 has a built in dedicated clock generator...

Lattice MachXO2 Timing errors.

New thread started 2 years ago
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...
@jt_eaton >We need to create an opensourced EDA tool chain using tools like kactus2 and have everyone support that.I would second that.
160 bits at 800 MHz - If my maths is correct, then that is about 800 x 1,000,000 x 160 which is 128 GBytes per second. Is that correct?This must be some pretty high-end...
@adamt99 - Thanks! This forum definitely seems to be full of kind and good natured people. It's a quite a marked difference to some of the others.

Re: Code review. Newbie's first verilog module!

Reply posted 6 years ago (03/24/2016)
Thanks - your points are really good.Magic numbers! I should've know that. Thinking about it, it might be better if I allow the current clock speed to be expressed...

Code review. Newbie's first verilog module!

New thread started 6 years ago
Hi This is one of the first verilog modules I wrote. It reads a 1-Wire iButton / Dallas keyfob code.The theory of operation is that approximately every two seconds...
Yes - @stephaneb I did that :-)
@cfelton - Thanks for the reply.I think I might push my head above the parapet and post some verilog code of mine here for review!
I think that it's the limitation of the tools that make it so troublesome. Bob Zeidman in his book "Introduction to Verilog" seems very much in favour of schematic...
I'm just a newbie when it comes to FPGA. I do have a few successful projects under my belt, but I'm not so brave to think that's enough to call myself an FPGA engineer.However,...

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