Aaron (@apanella)
If you are using Vivado (which you should be, for an Artix FPGA), then you can add a FIFO to your design by creating an IP block design and adding a FIFO. From...
VHDL for Logic Synthesis is a good book for learning VHDL in general. Can probably find a .pdf on google. My advice would be to learn these things within VHDL: -Types...
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