Markus Nentwig (@mnentwig)

Markus received his Dipl. Ing. degree in electrical engineering / communications in 1999. Work interests include RF transceiver system design, implementation, modeling, verification and nowadays production testing. He works for Qualcomm in Munich.

Spline interpolation

Markus Nentwig ● May 11, 2014●7 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

Signed serial-/parallel multiplication

Markus Nentwig ● February 16, 2014

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm

• A detailed discussion of bit-level trickstery in signed-signed multiplication
• Algorithm based on Wikipedia example
• Includes a Verilog implementation with parametrized bit width

A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...

Shared-multiplier polyphase FIR filter

Markus Nentwig ● July 31, 2013●6 comments

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...

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