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Re: Doubt about constraining external input

Reply posted 8 months ago (02/27/2021)
No, I meant DDS fsysclock as datasheet reports.In my case the DRG timebase would be around 104 MHz (DDS fsysclock = 2500 MHz).I am actually using an edge detector...

Re: Doubt about constraining external input

Reply posted 8 months ago (02/27/2021)
If the DRG time base is fsysclock/24 yes, DROVER can be sampled.

Doubt about constraining external input

New thread started 8 months ago
Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...

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