No, I meant DDS fsysclock as datasheet reports.In my case the DRG timebase would be around 104 MHz (DDS fsysclock = 2500 MHz).I am actually using an edge detector...
If the DRG time base is fsysclock/24 yes, DROVER can be sampled.
Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...
Use this form to contact simonzz
Before you can contact a member of the *Related Sites:
- You must be logged in (register here)
- You must confirm you email address