No profile info found for srid

DSP Filter Verification in FPGA

New thread started 4 years ago
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...

Use this form to contact srid

Before you can contact a member of the *Related Sites:

  • You must be logged in (register here)
  • You must confirm you email address