About wlarsen

Bachelors & Masters Degree from UMKC in electrical engineering. Currently working as an R&D engineer. Experience/training in Xilinx Vivado/SDK using the MicroBlaze and Zynq chipsets.

Generating a Block Design in Vivado from existing Verilog & IP files

New thread started 6 years ago
I have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there...

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