On Feb 22, 5:43=A0am, Michael <michael_laaja...@yahoo.com> wrote:
> Hi,
>
> How do I setup synopsys_sim.setup for simulating both Verilog and VHDL
> using VCS for a Xilinx FPGA?
>
> I need for instance have SIMPRIM point to both the VHDL and the Verilog
> compiled library path, I did try using a : and simply append them but it
> failed.
>
> /michael
have you tried using "vlog" to compile verilog codes and "vcom" to
compile VHDL codes?
Reply by Michael●February 21, 20122012-02-21
Hi,
How do I setup synopsys_sim.setup for simulating both Verilog and VHDL
using VCS for a Xilinx FPGA?
I need for instance have SIMPRIM point to both the VHDL and the Verilog
compiled library path, I did try using a : and simply append them but it
failed.
/michael