First CFP: The 12th World Congress on Information and Communication Technologies (WICT'22) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga1 week ago

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- The 12th World Congress on Information and...

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- The 12th World Congress on Information and Communication Technologies (W= ICT'22) -- http://www.mirlabs.org/wict22 http://www.mirlabs.net/wict22 On the World Wide Web December 15-17, 2022 Proceedings of WICT'22 will be published with Springer Verlag in their Lect= ure Notes in Networks a...


First CFP: 13th International Conference on Innovations in Bio-Inspired Computing and Applications (IBICA'22) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga2 weeks ago

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- The 13th International Conference on Innovations in...

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- The 13th International Conference on Innovations in Bio-Inspired Computing and Applications (IBICA'22) -- http://www.mirlabs.net/ibica22 http://www.mirlabs.org/ibica22 On the World Wide Web December 15-17,2022 Proceedings of IBICA'22 will be published with Springer Verlag in their Lecture ...


Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less resources than 64-bit version?

Started by Qiu Shui in comp.arch.fpga4 weeks ago 1 reply

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...


First CFP: 14th World Congress on Nature and Biologically Inspired Computing (NaBIC 2022) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga1 month ago

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- 14th World Congress on Nature and Biologically...

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- 14th World Congress on Nature and Biologically Inspired Computing (NaBIC= 2022) -- http://www.mirlabs.net/nabic22 http://www.mirlabs.org/nabic22 On the World Wide Web December 14-16,2022 Proceedings of NaBIC'22 will be published with Springer Verlag in their Lec= ture Notes in Networks ...


First CFP: 14th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2022) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga1 month ago

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- 14th International Conference on Soft Computing...

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- 14th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2022) -- http://www.mirlabs.org/socpar22 http://www.mirlabs.net/socpar22 On the World Wide Web December 14-16,2022 Proceedings of SoCPaR'22 will be published with Springer Verlag in their Lecture Notes in Net...


First CFP: 18th International Conference on Information Assurance and Security (IAS 22) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga1 month ago

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- 18th International Conference on Information...

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- 18th International Conference on Information Assurance and Security (IAS 2022) -- http://www.mirlabs.org/ias22 http://www.mirlabs.net/ias22 * On the World Wide Web * December 13-15, 2022 Proceedings of IAS'22 will be published with Springer Verlag in their Lecture Notes in Networks and...


First CFP: 22nd International Conference on Intelligent Systems Design and Applications (ISDA 2022) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga1 month ago

** First Call for Papers - please circulate this CFP to your colleagues= and networks ** -- The 22nd International Conference on...

** First Call for Papers - please circulate this CFP to your colleagues= and networks ** -- The 22nd International Conference on Intelligent Systems Design and Appl= ications (ISDA=E2=80=9922) =E2=80=93- http://www.mirlabs.org/isda22 http://www.mirlabs.net/isda22 On the World Wide Web December 12-14, 2022 Proceedings of ISDA'22 will be published with Springer Verlag in their...


First CFP: 22nd International Conference on Hybrid Intelligent Systems (HIS'22) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga2 months ago

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- The 22nd International Conference on Hybrid...

** First Call for Papers - please circulate this CFP to your colleagues and= networks ** -- The 22nd International Conference on Hybrid Intelligent Systems (HIS'22)= -- http://www.mirlabs.net/his22 http://www.mirlabs.org/his22 On the World Wide Web December 13-15, 2022 Proceedings of HIS'22 will be published with Springer Verlag in their Lectu= re Notes in Networks and Systems...


Development tools for Xilinx Spartan 3

Started by Stef in comp.arch.fpga3 months ago 4 replies

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer and ISE 9.2, both no longer available. New Vivado versions do not seem to support Spartan 3. What are the current options for making changes to a Spartan 3 design? -- Stef Facts are stubborn, but statistics are more pliable.


Calculation of throughput of sub-block in digital design (I)

Started by Hassan Iqbal in comp.arch.fpga3 months ago

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here...

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here are the few scenarios: 1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output. -> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle 2. DUT takes 10 clock cycles to ge


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