who knows how to make 480P HDMI output in VHDL code ?

Started by Anonymous in comp.arch.fpga2 days ago

code used from hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI

code used from hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI


Strange thing, my FPGA HDMI output cannot work with cheap chinese HDMI Extender

Started by Anonymous in comp.arch.fpga2 days ago 8 replies

I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA...

I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA board,there is a problem. I enabled TMDS, HPD, DDC, 5+, ground as in Hamsterwork's project , it doesnot works,I dont know why? Who had the same situation ? What to do ? Alibaba seller know nothing about this, but they always tell me they manufactu...


New(ish) FPGA Company

Started by Anonymous in comp.arch.fpga1 week ago 8 replies

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know...

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know much about them? http://www.anlogic.com/ Google can translate the web pages, but not the data sheets. Rick C.


FPGA Market Entry Barriers

Started by Anonymous in comp.arch.fpga3 weeks ago 57 replies

I was wondering what the barriers are to new companies marketing FPGAs. Some of the technological barriers are obvious. Designing a novel device...

I was wondering what the barriers are to new companies marketing FPGAs. Some of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feature. Silicon Blue exploited a low power technology optimized for low cost device


What to do with an improved algorithm?

Started by Mike Field in comp.arch.fpga1 month ago 18 replies

Hi, I think I've got a really good way to improve a commonly used & well establ= ished algorithm that is often used in FPGAs, and it all...

Hi, I think I've got a really good way to improve a commonly used & well establ= ished algorithm that is often used in FPGAs, and it all checks out. The imp= lementation completes the same tasks in 2/3rds the cycles and using 2/3rds = the resources of an standard Xilinx IP block, with comparable timing). I've verified that the output is correct over the entire range of 32-bit in= put val...


Need magic incantation to prevent synthesizer misoptimisation

Started by Aleksandar Kuktin in comp.arch.fpga1 month ago 2 replies

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following...

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog: reg [31:0] mem_dataintomem = 32'd0; always @(posedge CLK) begin if (mcu_active && (w_we_recv || w_tlb_recv)) mem_dataintomem


Schematic FPGA Design on twitch

Started by Anonymous in comp.arch.fpga2 months ago 2 replies

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out


Need Help regarding I2C Protocol testbench

Started by Swapnil Patil in comp.arch.fpga2 months ago 1 reply

Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state...

Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine. The problem with simulation result is that it is writing data properly but not reading it.I do not understand what is problem? here is my testbench Data in sent internally via array. ENTITY mainfiletb12 IS END mainfiletb12; ARCHITECTUR...


Need Advice regarding Interfacing of Max9850 audio DAC with spartan 6 FPGA

Started by Swapnil Patil in comp.arch.fpga2 months ago 1 reply

Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does...

Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does Someone worked on this before? or worked related to this. Things need to know I am using only these two for interfacing.So For clocking what should i do?(can i use fpga clock for driving master clock) what audio data format to choose?Right justifie...


System Verilog Import package error

Started by nikh...@gmail.com in comp.arch.fpga2 months ago

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- --...

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- -- endpackage package C; import A::*; import B::*; endpackage In the file using package C, the error I am getting is as follows: Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declaratio...


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