UDP -FPGA point to point

Started by Manav Nair in comp.arch.fpga2 days ago 3 replies

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between...

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening point to point so I was wondering do I need ARP implementation in my stack or can I just broadcast the message. I am building a UDP stack but was wondering is ARP a necessary requirement. Also, the ...


Is there any software I can use to transform state machines in VHDL into drawings?

Started by Tianxiang Weng in comp.arch.fpga2 weeks ago 6 replies

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is...

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in VHDL into drawings? Thank you. Weng


All my PDF files suddenly become Chrome HTML Document! Why?

Started by Tianxiang Weng in comp.arch.fpga3 weeks ago 3 replies

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng


Notepad++ is an excellent editor for coding VHDL

Started by Tianxiang Weng in comp.arch.fpga3 weeks ago 1 reply

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of how powerful Notepad++ is: In 27 files, I easily found that I use the statement "when others => null; " 119 times and the statement "end case;" 117 times. There are certainly 2 mismatches for the 2 types of statements. I found only 1 mismat


Xilinx forums have disappeared?

Started by Wojciech Zabolotny in comp.arch.fpga4 weeks ago 3 replies

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to https://support.xilinx.com/s/ . There is no forum available any more. Does it mean that all the knowledge created by the users is lost forever? If I remember it happened once in the past with Xilinx forum. Have they done it again? Reg...


GDB from my university...

Started by Yousaf tehseen in comp.arch.fpga2 months ago 2 replies

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated...

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated PAL can be programmed using ABEL (Advanced Boolean Expression Language) and VHDL (Verilog Hardware Descriptive Language). Which programming technology would you use to accomplish the task outlined considering the constraints given below?


PLL dynamic phase shift

Started by promach in comp.arch.fpga3 months ago

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png...

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png https://i.imgur.com/jgfvxk6.png


A state machine design problem

Started by Tianxiang Weng in comp.arch.fpga3 months ago 1 reply

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal...

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Output_State, Output_State_NS : Output_State_t ; At a clocked process, there is code with the Output_State: p1: process(Clock, Reset) begin if Reset then Output_State


Synthesis : Pan's Algorithm

Started by promach in comp.arch.fpga3 months ago

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3...

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3 https://i.imgur.com/GO8s4BU.png 1. How is Pan's algorithm being a shortest-path algorithm when clock period is computed across the critical path (longest path) ? 2. Any idea about the modified version of Pan's algorithm described in Figure 2 on page ...


Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less resources than 64-bit version?

Started by Qiu Shui in comp.arch.fpga4 months ago

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...


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