VHDL TIME support in Vivado

Started by Rob Gaddi in comp.arch.fpga2 weeks ago 12 replies

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to...

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time integer. https://www.xilinx.com/support/answers/57964.html is from 2014. Five years. In five years, Xilinx has remained unable to perform simple division. Absolutely embarrassing. -- Rob Gaddi...


Bayer Pattern to RGB VHDL CODE

Started by Anonymous in comp.arch.fpga2 weeks ago 1 reply

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer...

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ?


Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking?

Started by Weng Tianxiang in comp.arch.fpga2 weeks ago 3 replies

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a...

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine....


New uses of FPGAs

Started by Anonymous in comp.arch.fpga4 weeks ago 10 replies

FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules?

FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules?


Field update

Started by Jan in comp.arch.fpga1 month ago 10 replies

Dear all, What are the smartest way to make a solo FPGA project capable of field updates? I'm very new in the FPGA world so I don't much...

Dear all, What are the smartest way to make a solo FPGA project capable of field updates? I'm very new in the FPGA world so I don't much about the practical use of them. Normally when I uses microcontrollers I make them updateble via USB, serial or SD cards. What techniques are possible when I want to avoid having a uP in the project. My target is a Xilinx Spartan 3A or 3AN Reg...


Lattice XO3D New

Started by Rick C in comp.arch.fpga1 month ago

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB...

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB fabrication with the need for fine pitch and very small vias. These devices seem to be aimed at products requiring high security, but the other aspects suit me to a tee. There are two size devices, about 4000 LUTs and about 9000 LUTs


Unique uses for the DSP48

Started by Kevin Neilson in comp.arch.fpga2 months ago 8 replies

I've tried to figure out how to use the Xilinx DSP48s for Galois arithmetic, but they really aren't that useful for that. The new ones can do a...

I've tried to figure out how to use the Xilinx DSP48s for Galois arithmetic, but they really aren't that useful for that. The new ones can do a 96-bit unary XOR, which can be used for GF(2) matrix multiplication, but the multipliers themselves aren't of much use for Galois math. I wondered what unusual uses (besides FIR filters or integer matrix multipliers) people have used these


How do big compagnies use Verilog/VHDL for processor designs?

Started by Benjamin Couillard in comp.arch.fpga2 months ago 2 replies

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example, if they implement an...

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do they instantiate hand-optimized components (adder, barrel shifter, multiplier). Basically, does the synthesizer actually do something or does it only connect hand-optimized components? Regards ...


HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

Started by Anonymous in comp.arch.fpga2 months ago 1 reply

There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit...

There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit image is divided into 8bit. The problem I'm facing is I don't know how to read a single reg in 2 clock cycles i.e. 32bit in one cycle and remaining 32bit in second cycle. I'll be grateful if you can help me out with it. Thankyou.


bare-metal ZYNQ

Started by John Larkin in comp.arch.fpga2 months ago 25 replies

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot...

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD card, whatever) and reads in a secondary boot program, which the Xilinx tools provide as part of a build. That loader then reads the entire FPGA config bitstream into DRAM, and sets up a gi...


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