AGM AG6K SoC

Started by Rick C in comp.arch.fpga2 hours ago

I found the part I had been interested in, the AGM AG6K SoC with a 250 MHz = ARM Cortex processor, 6,000 LE FPGA, 128 kB SRAM, 12 bit ADC, all in...

I found the part I had been interested in, the AGM AG6K SoC with a 250 MHz = ARM Cortex processor, 6,000 LE FPGA, 128 kB SRAM, 12 bit ADC, all in a 100 = pin QFP package. Works for many of my apps although these days I'd prefer = an 88 pin QFN I think. Good density and still works with 6/6 mil design ru= les, but it has that thermal pad in the center while makes vias difficult u= nderneath ...


Gowin Semiconductor, Real or Fake?

Started by Rick C in comp.arch.fpga15 hours ago 6 replies

On 13/11/2019 07:47, Rick C wrote: > On Tuesday, November 12, 2019 at 4:10:10 AM UTC-5, Michael Kellett wrote: > > On 12/11/2019 01:09, Brane2...

On 13/11/2019 07:47, Rick C wrote: > On Tuesday, November 12, 2019 at 4:10:10 AM UTC-5, Michael Kellett wrote: > > On 12/11/2019 01:09, Brane2 wrote: > > > You might be interested in gowin's program, especially their LittleBee series. > > > > > > To me, it looks like they've nailed. > > > > > > To me, this is everything that MachXO3 should have been... > > > > > > https://www.gowinsemi.com/en/ > > >


Lattice XO3D New

Started by Rick C in comp.arch.fpga3 days ago 7 replies

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB...

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB fabrication with the need for fine pitch and very small vias. These devices seem to be aimed at products requiring high security, but the other aspects suit me to a tee. There are two size devices, about 4000 LUTs and about 9000 LUTs


FPGA config sizes

Started by John Larkin in comp.arch.fpga4 days ago 13 replies

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an...

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations. So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application? I think we could enable compression too. ...


Lattice MachXO2/XO3/XO3D vs ECP5

Started by Brane2 in comp.arch.fpga1 week ago 2 replies

Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-low end of their product...

Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-low end of their product lines, but simple 6900 LUT XO3 is significantly more expensive than 12kLUT ECP5. What gives ?


Tiny CPUs for Slow Logic

Started by Anonymous in comp.arch.fpga3 weeks ago 72 replies

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA...

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks. There are stack based processors that are very small, smaller than even a few kB of memory. If they were easily programmable in something other than C would anyone be interested?


Student seeking for Internship in Digital Design

Started by Joshua Roy in comp.arch.fpga2 months ago

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been...

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been experimenting on my Artix-7 Basys-3 board since my 2nd-semester and got very fascinated in the field of digital architecture designing. Since then, I have been involved in a number of projects related to this field. It is my request that if any opportunit...


Here is new definition for keyword "if_2", version 2.

Started by Weng Tianxiang in comp.arch.fpga2 months ago 12 replies

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: " New keyword "if_2" is...

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: " New keyword "if_2" is suggested for dealing with 2-write port memory." New keyword "if_2" is used to put m-write and n-read memory module from chip manufactures' toolbox behind HDL language so that with the new keyword "if_2" introduction any m-write and n-read memo


How to write a correct code to do 2 writes to an array on same cycle?

Started by Weng Tianxiang in comp.arch.fpga2 months ago 12 replies

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK)...

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 then An_Array(a)


New keyword "if_2" for HDL is suggested for dealing with 2-write port memory

Started by Weng Tianxiang in comp.arch.fpga2 months ago 5 replies

Hi, In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in...

Hi, In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications. To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "


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