PLL dynamic phase shift

Started by promach in comp.arch.fpga4 days ago

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png...

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png https://i.imgur.com/jgfvxk6.png


A state machine design problem

Started by Tianxiang Weng in comp.arch.fpga4 weeks ago 1 reply

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal...

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Output_State, Output_State_NS : Output_State_t ; At a clocked process, there is code with the Output_State: p1: process(Clock, Reset) begin if Reset then Output_State


Synthesis : Pan's Algorithm

Started by promach in comp.arch.fpga4 weeks ago

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3...

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3 https://i.imgur.com/GO8s4BU.png 1. How is Pan's algorithm being a shortest-path algorithm when clock period is computed across the critical path (longest path) ? 2. Any idea about the modified version of Pan's algorithm described in Figure 2 on page ...


Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less resources than 64-bit version?

Started by Qiu Shui in comp.arch.fpga1 month ago

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...


How long does it take to fill up an array prior to sorting?

Started by Kevin Simonson in comp.arch.fpga1 month ago 4 replies

Most sorting algorithms I've noticed seem to have an interface somewhat like this: void someAlgorithm ( elemType[] elements); So to...

Most sorting algorithms I've noticed seem to have an interface somewhat like this: void someAlgorithm ( elemType[] elements); So to implement this algorithm an application needs to fill the {elements} array, call the {someAlgorithm()} algorithm, and then read out the (sorted) elements of {elements}. For an {elements} object that contains n {elemType}s, how long does it take to fi


A loop problem which does not do what is expected

Started by Tianxiang Weng in comp.arch.fpga1 month ago 9 replies

Hi, I have a problem that does not do what is expected. I have several modules linked together from top to bottom. Each module has 3 error...

Hi, I have a problem that does not do what is expected. I have several modules linked together from top to bottom. Each module has 3 error output signals: Error_O, Error_Level_O, and Error_Code_O. If a module has an error, Error_O = '1', Error_Level_O and Error_Code_O have their proper error info. There are 3 arrays to correct that information from each of those modules: Error_O_m(), Error_...


How to increase data of std_logic_vector by 1 in VHDL-2002

Started by W TX in comp.arch.fpga1 month ago 8 replies

Hi, It is a long time headache for me to increase a data of std_logic_vector by 1. Here are examples: LIBRARY ieee; USE...

Hi, It is a long time headache for me to increase a data of std_logic_vector by 1. Here are examples: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; constant ONE : std_logic_vector(7 downto 0); signal Series_Number : std_logic_vector(7 downto 0); ... All followings generate errors in VHDL-2002: Series_Number


Measuring ps of delays in FPGAs

Started by partha sarathy in comp.arch.fpga1 month ago

Hi FPGA Experts, How can we measure ps of delays in FPGA with minimum area and good accuracy ? Today's TDC (Time to Digital Converter)...

Hi FPGA Experts, How can we measure ps of delays in FPGA with minimum area and good accuracy ? Today's TDC (Time to Digital Converter) architectures suffer lot of drawbacks like high gate utilization, High number of delay cells required for high resolution, Longer dead time, dependant on PVT conditions etc. Regards Parth


Enterpoint dev board manuals

Started by Philip Pemberton in comp.arch.fpga2 months ago

Hi folks, It looks like Enterpoint (www.enterpoint.co.uk) has closed down. I've got one of their Drigmorn2 dev boards and some of the addon...

Hi folks, It looks like Enterpoint (www.enterpoint.co.uk) has closed down. I've got one of their Drigmorn2 dev boards and some of the addon modules. Does anyone have a copy of these documents? - Ethernet PHY schematic (ETHERNET_PHY_V2.pdf or ETHERNET_PROJECT.pdf) - Cy7C68014 USB2 Slave module schematic (USB_SLAVE_MODULE.pdf) Sadly they're missing from the Internet Archive version of thei...


How to eliminate a troublesome warning from ModelSim

Started by Tianxiang Weng in comp.arch.fpga2 months ago

Hi, From the first day when I started using ModelSim, a troublesome warning from ModelSim accompanies me each time I use ModelSim. I use...

Hi, From the first day when I started using ModelSim, a troublesome warning from ModelSim accompanies me each time I use ModelSim. I use Notepad++ to edit my *.vhd files, after recompiling the files, it always shows the following error report: # Compile of *.vhd was successful. # ** Error: # g # Unable to replace existing ini file (xxx.mpf). File can not be renamed. # ** Error:...


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