8 bits vs. 9 bits in RAM Blocks

Started by Anonymous in comp.arch.fpga2 weeks ago 4 replies

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have...

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. Does this make much of a difference to you? Do you use the 9 bit widths in your designs? Rick C.


Stepper motor controller

Started by Anonymous in comp.arch.fpga2 weeks ago 2 replies

Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc....

Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc. How i can make give position back.. I.E. I want to give position to stepper motor controller not push a button.. could some one help me with code ?


We are looking for invited speakers for our conferences and seminars: 5th Reconfigurable Market

Started by UMons SEMI in comp.arch.fpga2 weeks ago

We are looking for invited speakers for our conferences and seminars. Our main interest will be talks about reconfigurable market (FPGA)....

We are looking for invited speakers for our conferences and seminars. Our main interest will be talks about reconfigurable market (FPGA). But we are having problems getting their names and contact email. We would like to have talks from Xilinx, Intel/Altera, Google, Amazon, IBM, etc. We would like to build a list of people to contact and invite locally (Belgium), Europe and


How to analyes IBERT ip results for highspeed signals?

Started by yogesh tripathi in comp.arch.fpga1 month ago

Hi, I just started working with IBERT ip from xilinx. Can anyone suggest some references to look into to analyse the ip results and how to...

Hi, I just started working with IBERT ip from xilinx. Can anyone suggest some references to look into to analyse the ip results and how to adjust the proper 2d eye scan? Thank-You in advance.


How to chnge this VHDL code into Verilog code

Started by Haimanot Tizazu in comp.arch.fpga2 months ago 1 reply

architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type...

architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0); -- Round constants for each round constant rcs: round_constants := (x"0000000000000000", x"13198A2E03707344", ...


Searching for info about very old FPGA devices

Started by Rodrigo Melo in comp.arch.fpga2 months ago 7 replies

Hello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google,...

Hello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google, archive.org, alldatasheets, and more places...). I obtained name from old papers and patents: * Plessey (1989). ERA60100 Preliminary Datasheet. Plessey Semiconductor, Swindon, England. * GEC Plessey Semiconductors, ERA60100 Electrically Reconfigu


Can a glitch-free mux be designed in an FPGA?

Started by Mr.CRC in comp.arch.fpga2 months ago 14 replies

Hi: The simplest incarnation of a 2-to-1 multiplexer can be described by the equation: y = ~s & a | s & b where 'y' is the output, 's'...

Hi: The simplest incarnation of a 2-to-1 multiplexer can be described by the equation: y = ~s & a | s & b where 'y' is the output, 's' is the select input, with 'a' and 'b' the data inputs. Of course, this multiplexer is broken because a practical implementation glitches in a if 'a' and 'b' are true, and the select line toggles. Such as this example from the book (1): -----------...


Communication between HDL simulation and user software via ZMQ

Started by Anonymous in comp.arch.fpga2 months ago

I develop systems were the FPGA-based hardware will use message-based communication (via Ethernet, USB or another communication channel) with...

I develop systems were the FPGA-based hardware will use message-based communication (via Ethernet, USB or another communication channel) with remote software. Those systems require thorough testing in simulations. Therefore I needed to create a mechanism for communication between the simulation and software using the remote message-passing library like ZeroMQ. The first version was


CPLD 1.8V to 3.3V bidirectional SDA

Started by nobody in comp.arch.fpga2 months ago 10 replies

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and...

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and fsync. Voltage level on the sensor board is 1.8V the PI is 3.3V. I have CPLD hardware that I would like to use to make the bidirectional level shifted SDA as well as level shift the other three. The VHDL behavior is as simple as: begin en


FPGA selection recommendation

Started by Piotr Wyderski in comp.arch.fpga2 months ago 25 replies

I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like...

I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like to connect it to a 16-bit DRAM, so there should exist a memory controller with this feature, either a hard macro or a soft IP core. There should also be a fast ethernet MAC. Nothing fancy, but: 1. This is for a small non-profit project, so the IP...


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