initializing a small array in Verilog

Started by David Bridgham in comp.arch.fpga4 days ago 3 replies

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and...

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and it does what I expect. However, I recently discovered Verilator and its lint capability so I've been running it over all my code to see if there is anything I ought to clean up. Verilator does not like this code, it says the LHS only has 2 bits wh...


Need help to understand: Efficient Multi-Ported Memories for FPGAs

Started by Weng Tianxiang in comp.arch.fpga5 days ago 24 replies

Hi, I cannot understand the following paper: "Efficient Multi-Ported Memories for FPGAs"...

Hi, I cannot understand the following paper: "Efficient Multi-Ported Memories for FPGAs" http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read. The paper essence for 2 write ports and 2 read ports ...


Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Started by Weng Tianxiang in comp.arch.fpga1 week ago 68 replies

Hi, Can I use Verilog or SystemVerilog to write a state machine with clock gating function? I know VHDL has no such function and want to...

Hi, Can I use Verilog or SystemVerilog to write a state machine with clock gating function? I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine. Thank you. Weng


Estimating ROM gate count in ASIC

Started by Kevin Neilson in comp.arch.fpga2 weeks ago 12 replies

I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estimate of the gate count of a...

I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estimate of the gate count of a lookup ROM implemented in ASIC gates. Yes, I know it's dependent on the contents. However, if half the bits are ones and the contents are randomly distributed, a formula should be pretty accurate. It's easy for me to figure out an


What is the name of the circuit structure that generates a state machine's jumping signals?

Started by Weng Tianxiang in comp.arch.fpga4 weeks ago 45 replies

Hi, What is the name of the circuit structure that generates a state machine's jumping signals? I remember I looked at the circuit structure...

Hi, What is the name of the circuit structure that generates a state machine's jumping signals? I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. What is the correct name? Thank you. Weng


How to make Altera-Modelsim free download version to work?

Started by Weng Tianxiang in comp.arch.fpga4 weeks ago 35 replies

Hi, I downloaded 11.0_modelsim_ase_windows.exe...

Hi, I downloaded 11.0_modelsim_ase_windows.exe from https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html Release Notes For ModelSim Altera 10.1b Apr 26 2012 Copyright 1991-2012 Mentor Graphics Corporation All rights reserved. After installing the software, I cannot run it:...


How to write an "alias" statement

Started by Weng Tianxiang in comp.arch.fpga2 months ago 4 replies

Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for...

Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. Here is code defining the register array R: type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0); signal R : R_Type; alias P1 : it shows R array part of (DATA_BITS-1 downto 0); alias P2 : i...


Why choose a IOT smart digital lock?

Started by Anonymous in comp.arch.fpga2 months ago

Smart locks are sure to become every homeowner’s favorite. They offer the same level of security as typical mechanical door locks, but...

Smart locks are sure to become every homeowner’s favorite. They offer the same level of security as typical mechanical door locks, but provide a range of alternatives to the mechanical key, and a host of other features. Digital locks are changing our lifestyle, leading us to a new digital era of keyless locking! Get Sample For Smart Lock: http://bit.ly/2RnrJL3 Authenticati


Engineer for Xilinx Zinq in Barcelona

Started by Jose Miguel in comp.arch.fpga2 months ago

Contact me!! At jmibanez@jeanologia.com

Contact me!! At jmibanez@jeanologia.com


Now - not so new cheaper FPGAs

Started by rickman in comp.arch.fpga2 months ago 5 replies

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is...

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is still trying to get rid of them. Seems they over estimated the market. I had to pay a higher price to them in 2016 than I paid when they were in production (~$10) but now they are going for around $5-$6 depending on quantity and they still have 65,...


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