I need to generate a programming file for an older XC7300 series chip using an existing Abel and/or PLD file. As far I know, only XactStep 6 and...

I need to generate a programming file for an older XC7300 series chip using an existing Abel and/or PLD file. As far I know, only XactStep 6 and Foundation 1.3 supported those chips as Foundation 1.4 doesn't have options for them any more. I have hardware dongles for the software but no license file so a couple of questions :). 1) Do the hardware dongles still require a LICENSE.DAT file? I kno...

I Need Help To Solve This project Need to write FPGA Source code

I Need Help To Solve This project Need to write FPGA Source code

This is a bit of the chicken and egg thing. If you want a embed the code checksum in a code module to report the checksum, is there a way of...

This is a bit of the chicken and egg thing. If you want a embed the code checksum in a code module to report the checksum, is there a way of doing this? It's a bit like being your own grandfather, I think. I'm not thinking anything too fancy, like a CRC, but rather a simple modulo N addition, maybe N being 2^16. I keep thinking of using a placeholder, but that doesn't seem

The space sector and cybersecurity are both evolving rapidly, with disrupti= ve technologies such as Low Earth Orbit (LEO) constellations,...

The space sector and cybersecurity are both evolving rapidly, with disrupti= ve technologies such as Low Earth Orbit (LEO) constellations, reconfigurabl= e satellites, critical services security, cloud computing, artificial intel= ligence and post-quantum cryptography. Please join us for an open discussion with cyber security leaders that will= address and present different angels of secur...

Are you tired of worrying about the security of your FPGA/ASIC system?=20 Allow me to introduce Xiphera FPGA/ASIC cryptographic IP =E2=80=93 a...

Are you tired of worrying about the security of your FPGA/ASIC system?=20 Allow me to introduce Xiphera FPGA/ASIC cryptographic IP =E2=80=93 a powerf= ul solution that secures your system on chip design, from data transmission= to user authentication.=20 Our IP=E2=80=99s are designed to seamlessly integrate with your FPGA/ASIC, = ensuring maximum security with minimal impact on performance. ...

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a...

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a way to obtain old versions? You cannot download from the site anymore. Chris

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free...

Hi, Overnight all my PDF files suddenly become Chrome HTML Document! Why? Are there some new things happening with Adobe policy on their free Read DC software yesterday? Thank you. Weng

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my...

A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find tha

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing...

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing projects impossible. Is it a problem with my browser (Firefox on Linux) or with the website? Regards, Wojtek

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx...

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx ! module Decimal_to_E3(input[10:0] dec, output reg[15:0] E3); reg[10:0] aux; reg[1:0] counter; always @ (dec) begin aux = dec; E3 = {4{4'b0011}}; counter = 2'b00; while(aux != 0) begin E3[counter * 4 +: 4] = aux % 10 + 3; aux = aux / 10; coun...