Reply by Kevin Neilson●February 21, 20132013-02-21
On Saturday, November 17, 2012 7:55:00 PM UTC-5, fl wrote:
> Hi,
>
>
>
> I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code:
>
>
>
> assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 :
>
> (cur_count == 2 && clk_enable == 1'b1)? 1 :
>
> ...
Another alternative for rewriting this more clearly is to use the Verilog 'inside' operator (now supported by Synplify):
assign ce_hciccomp_decode = clk_enable && cur_count inside {0,2,4,7,10,...61};
-Kevin
Reply by Gabor●November 19, 20122012-11-19
glen herrmannsfeldt wrote:
> rickman <gnuarm@gmail.com> wrote:
>> On 11/17/2012 7:55 PM, fl wrote:
>>> I know some VHDL, but totally new to verilog. Now I am reading
>>> a verilog template. I do not know the meaning of the following code:
>
> (snip)
>
>> This is something like an address compare with an enable. So the output
>> will be a 1 when any of the cur_count compares match and the clk_enable
>> is 1.
>
>> There are a couple of ways this could have been done with less typing.
>> The logic is a series of compares and then the clk_enable is really just
>> one enable to the whole thing. So why not code it similarly? For example,
>
>> assign ce_hciccomp_decode = (clk_enable == 0'b1) ? 0 :
>> (cur_count == 0) ? 1 :
>> (cur_count == 2) ? 1 :
>> (cur_count == 4) ? 1 :
>> (cur_count == 7) ? 1 :
>> ...
>> (cur_count == 61) ? 1 : 0;
>
>> Personally I think this is a lot more clear as well as less typing.
>
> But how about instead:
>
> assign ce_hciccomp_decode = (clk_enable == 0'b1) && (
> (cur_count == 0) ||
> (cur_count == 2) ||
> (cur_count == 4) ||
> (cur_count == 7) ||
> ...
> (cur_count == 61) );
>
> The conditional operator is nice when you have a value wider than
> one bit, or sometimes a more complicated expression, but doesn't
> help much (especially in readability) in cases like this.
>
> Have you ever seen C code like:
>
> if(x>0) y=1;
> else y=0;
>
> or:
>
> y=(x>0) ? 1:0;
>
> When you could write instead: y=(x>0);?
>
> -- glen
There's lots of ways to skin a cat...
Whenever I see a huge pile of ? : operators in an assignment, my
first impression is that someone really wanted to use a case
statement, but of course in Verilog that means changing the
wire to a reg and using an always @* process. For those who
started with Verilog before Verilog 2001, the sensitivity list
may have been seen as more work than coding it this way.
How about:
reg ce_hciccomp_decode;
always @*
case (cur_count)
2, 4, 7, 10, 13, 16, 18, 20,
22, 24, 26, 29, 32, 34, 36,
38, 40, 42, 45, 48, 50, 52,
54, 56, 58, 61: ce_hciccomp_decode = clk_enable;
default: ce_hciccomp_decode = 0;
endcase
-- Gabor
Reply by glen herrmannsfeldt●November 18, 20122012-11-18
rickman <gnuarm@gmail.com> wrote:
> On 11/17/2012 7:55 PM, fl wrote:
>> I know some VHDL, but totally new to verilog. Now I am reading
>> a verilog template. I do not know the meaning of the following code:
(snip)
> This is something like an address compare with an enable. So the output
> will be a 1 when any of the cur_count compares match and the clk_enable
> is 1.
> There are a couple of ways this could have been done with less typing.
> The logic is a series of compares and then the clk_enable is really just
> one enable to the whole thing. So why not code it similarly? For example,
> Personally I think this is a lot more clear as well as less typing.
But how about instead:
assign ce_hciccomp_decode = (clk_enable == 0'b1) && (
(cur_count == 0) ||
(cur_count == 2) ||
(cur_count == 4) ||
(cur_count == 7) ||
...
(cur_count == 61) );
The conditional operator is nice when you have a value wider than
one bit, or sometimes a more complicated expression, but doesn't
help much (especially in readability) in cases like this.
Have you ever seen C code like:
if(x>0) y=1;
else y=0;
or:
y=(x>0) ? 1:0;
When you could write instead: y=(x>0);?
-- glen
This is something like an address compare with an enable. So the output
will be a 1 when any of the cur_count compares match and the clk_enable
is 1.
There are a couple of ways this could have been done with less typing.
The logic is a series of compares and then the clk_enable is really just
one enable to the whole thing. So why not code it similarly? For example,
assign ce_hciccomp_decode = (clk_enable == 0'b1) ? 0 :
(cur_count == 0) ? 1 :
(cur_count == 2) ? 1 :
(cur_count == 4) ? 1 :
(cur_count == 7) ? 1 :
...
(cur_count == 61) ? 1 : 0;
Personally I think this is a lot more clear as well as less typing.
Rick
Reply by glen herrmannsfeldt●November 18, 20122012-11-18
fl <rxjwg98@gmail.com> wrote:
> I know some VHDL, but totally new to verilog. Now I am
> reading a verilog template. I do not know the meaning
> of the following code:
It is similar to the conditional operator in C, but in a continuous
assignment statement.
That said, I don't know why anyone would do it that way.
It seems much more obvious to do with || instead.
-- glen
Reply by BobH●November 18, 20122012-11-18
The assign statement is one of the ways used to implement combinational
logic (as opposed to registered logic). The basic syntax of what you
have here is:
assign out = condition ? true_data : false_data;
If condition is true, out gets the value true_data, else it gets the
value false_data.
So if cur_count is equal to one of the numerical values listed and
clk_enable is equal to 1 at the same time, the ce_hciccomp_decode gets
1, else it gets 0.
Regards,
BobH
On 11/17/2012 5:55 PM, fl wrote: