Hi Svenn,

> Shit, I need a native USB 2.0 host in VHDL. Any poor sucker who would do
> a 4 week job at USD30/week? Cash on Delivery!!!! (though paypal)
>=20
> Is this how we want globalization to work?

It is not in my best interest to let globalization work this way:) My hourl=
y and not weekly rate is typically around USD 30. Greek clients would be ha=
ppy having me work for USD 10 per hour, but I ditch them (like four times s=
ince September for some major projects -- like OEMs for license plate recog=
nition -- since there is no margin for any benefit!) So clients are helples=
s and are typically middle-men who want to go into production (yeah right, =
thanks for the entertainment Greek IT people!)

For these kind of tasks a reasonable hourly rate e.g. in Germany is around =
70-100 USD; this is what the client expects to pay for high-quality work.=
=20

I'm afraid that rates of a couple of dollars exist; don't ask me where, you=
 know. But in some aspect or another you will get what you pay for.


Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com
http://www.ajaxcompilers.com
http://www.perfeda.gr

Nikolaos Kavvadias wrote:

> Seems so. This guy was also in freelancer (which implies that I was there, too).
>
> Most freelancers offered around 30 USD per divider topology, which is about the cost
> of a casual (low-cost) dinner for two in Greece. But this is week's
> payment in a number of countries around the globe.
>

Shit, I need a native USB 2.0 host in VHDL. Any poor sucker who would do
a 4 week job at USD30/week? Cash on Delivery!!!! (though paypal)

Is this how we want globalization to work?

-- 
Svenn

> So, this is homework?
> 
> Tim Wescott
> Wescott Design Services

Seems so. This guy was also in freelancer (which implies that I was there, too).

Most freelancers offered around 30 USD per divider topology, which is about the cost of a casual (low-cost) dinner for two in Greece. But this is week's payment in a number of countries around the globe.

On Mon, 04 Nov 2013 12:51:45 -0800, Kristo Godari wrote:

> I forgot to say that i can't use '/' or '%'.And i can't change the
> module structure the module must have 2 inputs and 2 outputs:
> 
> module divider(
>   output reg[7:0] q,
>   output reg[7:0] r,
>   input [7:0] a,b);
> 
> /*
>   Code goes here
> */
> 
>  endmodule

So, this is homework?

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Am Mittwoch, 6. November 2013 08:52:16 UTC+1 schrieb Nikolaos Kavvadias:
> I am very interested to know which of the current RTL tools has a module generator for division. It would be a strong asset. 

Check out designware for Synopsys design compiler.

regards Thomas

Hi Glen,

> What is wrong with the combinatorial one? 

There is nothing wrong with the combinational divider in principle. 

Eventually, for use in an IP-based scheme, inputs and outputs would be registered. For standalone use/experimentation it is OK.

One would cascade maybe 1 or 2 iterations of either NR or Goldschmidt and this would be fine especially for such small datapath size. I guess a LUT-based scheme would also do.

> Also, that is what verilog would generate if it synthesized
> the / operator.  (I presume some do now, especially for only
> eight bits.)

I am very interested to know which of the current RTL tools has a module generator for division. It would be a strong asset. 

For instance, tools don't have a module generator for integer modulo (apart from trivial cases). I have an implementation of a very good algorithm (published in 2011) for variable and constant modulo: 

http://nkavvadias.com/eshop/index.php?id_product=9&controller=product
https://groups.google.com/forum/#!msg/comp.lang.verilog/7ei2AKq6_Es/7vLHSCkTg3UJ

It is a pay IP alright, but the product brief and documentation are free for downloading. Any of the A, X, L, M, or S companies should provide such module generators in their backend tools.


Best regards
Nikolaos Kavvadias

Nikolaos Kavvadias <nikolaos.kavvadias@gmail.com> wrote:
 
> what we have here is both a lazy teacher giving an understated 
> assignment, and the typical student of this decade, looking the 
> easy way through. As most of 20ers are these days, he needs time 
> for WoW, tablet time, txting, net news or whatever.

Well, it is presumable in the context of what was taught in class,
which we don't know. 
 
> I would start with an untimed version in C, then devise 
> the FSM/FSMD and do the work. Shouldn't be more than an 
> afternoon for each subtask for a student. Of course, 
> this requires to wake up the teacher and ask him whether 
> he really requests a combinational implementation or would 
> allow for a clock.

What is wrong with the combinatorial one? 

They tend to take more hardware, as you can't time-share
(reuse) parts of the logic, but there is nothing wrong with that.

Seems to me that one should learn the combinatorial one first.

Also, that is what verilog would generate if it synthesized
the / operator.  (I presume some do now, especially for only
eight bits.)

Now, often in actual practice one wants either the pipelined
or iterative algorithm, but one should be able to understand
any and all of them.

-- glen

Hi all,

what we have here is both a lazy teacher giving an understated assignment, =
and the typical student of this decade, looking the easy way through. As mo=
st of 20ers are these days, he needs time for WoW, tablet time, txting, net=
 news or whatever.

I would start with an untimed version in C, then devise the FSM/FSMD and do=
 the work. Shouldn't be more than an afternoon for each subtask for a stude=
nt. Of course, this requires to wake up the teacher and ask him whether he =
really requests a combinational implementation or would allow for a clock.


Best regards
Nikolaos Kavvadias

Thomas Stanka <usenet_nospam_valid@stanka-web.de> wrote:
> Am Montag, 4. November 2013 15:48:28 UTC+1 schrieb Kristo Godari:
>> I need a Verilog behavioral model (verilog behavioral code) for:
>> - unsigned 8-bit division 
 
> behavioral model means not necessary synthesisable. 

This is true, and I prefer structural verilog, but enough is
synthesizable that many do write behavioral model for synthesis.

> Easiest is a = b/c.
> Your teacher don't like you to use this easiest sollution, 
> so he requestst you to learn about additional algorithms and 
> write them down.

Since there is no clock, it has to be all combinatorial logic.
I find continuous assignment more readable for combinatorial
logic than behavioral assignment. On the other hand, I like to
read state machines in behavioral form, where there is a latch
on every state transition.

-- glen

Hello,

Am Montag, 4. November 2013 15:48:28 UTC+1 schrieb Kristo Godari:
> I need a Verilog behavioral model (verilog behavioral code) for:
>
> - unsigned 8-bit division 

behavioral model means not necessary synthesisable. 
Easiest is a = b/c.
Your teacher don't like you to use this easiest sollution, so he requestst you to learn about additional algorithms and write them down.

Forget about pipelining, clock etc.
Have a look at the suggested algorithms and translate them in verilog code.

bye Thomas