The Memory Corner on xilinx.com (
http://www.xilinx.com/products/design_resources/mem_corner/index.htm ) has
good information on timing analysis for ZBT designs, along with some new
Spartan-3 app notes.

Most of the data sheet and speed file parameters are relative to the pins
on a given logic block (including device pins for the IOB block).  An
example is Tiockp, which is measured from the clock input on the IOB to
the output pin.  Some parameters are between two device pins, such as
Tickofdcm, which includes the clock input IOB, the path through the DCM
and the clock routing, and finally the Tiockp block delay to the output
pin.  If that's the path you're going to use, it's much more meaningful to
have all the delays added together for you than just looking at individual
block delays.

You are correct that typically higher drive provides higher performance,
but there can be exceptions.  Note that we have made some modifications to
these numbers in the latest speed file and for your device the 16 mA and
24 mA outputs are slightly faster than 12 mA.  The speed file is always
the most specific and the most accurate, and was just updated in v1.32
from Advance for the XC3S200 -4, which is now in production.

Andrew wrote:

> Hi,
> Im calculating the memory bandwidth achievable when interfacing a
> Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT
> SRAM (128k x 36bit). In general I have found the Spartan 3 datasheet
> very good (I like the text/description column in the switching
> characteristics section of the datasheet) but in the following
> instance I am stuck (probably due to my lack of understanding rather
> than the datasheet.)
>
> To do the memory bandwidth timing calculation I need to know the
> following FPGA IOB timing:
> 1)the clock to out delay for the IOB OFF(output flipflop) and
> 2)setup time for the IOB IFF(input flipflop).
>
> Finding 1) from the datasheet:
> I found table 12 on page11 of the DC and switching characteristics
> section. The "pin to pin clock to output time for the IOB output path"
> is Tickofdcm = 2.59ns. (DCM in use) But then when I look deeper into
> the datasheet I also find table 17 on pg 16 called Timing for the IOB
> output path. Tiockp gives a clock to output time of 4.18ns.  What is
> the difference between these two timing paramaters? What I want to
> know is the time from a rising edge on OFF's OTCLK to the data bit
> appearing at the FPGA Pin on the PCB.
>
> Finding 2) from the datasheet:
> Table 13 on pg 12 is called "pin to pin setup and hold times for the
> IOB input path". Tpsdcm = 2.72ns is the relevant parameter.
> But then table 14 "Setup and hold times for the IOB input path" show
> Tiopick = 1.32ns.  Which of these two timing parameters should I use?
> what is the difference?
>
> Notes:
> The IO standard used is LVCMOS25
> I am using Spartan 3 datasheet DS099, march 4, 2004.
>
> I also noticed an interesting thing in table 19, output timing
> adjustments for IOB, LVCMOS25 FAST. The 16mA and 24mA drivers are
> slower than the 12mA drivers? I expected them to be faster.
>
> Also noticed the datasheet seems to be "advance product specification"
> which according to the datasheet is described as "These specifications
> are based on simulations only...." Scary stuff.  Is there a more
> appropriate place I should be getting my timing numbers from, e.g.
> download latest speed files and use timing analyzer? Is the
> documentation just out of date? They must have characterized the
> production silicon right?
>
> Regards
> Andrew

--
Marc Baker
Xilinx Applications
(408) 879-5375

Hi,
Im calculating the memory bandwidth achievable when interfacing a
Xilinx Spartan 3 (XC3S200, -4 speedgrade) with a Samsung 133MHz ZBT
SRAM (128k x 36bit). In general I have found the Spartan 3 datasheet
very good (I like the text/description column in the switching
characteristics section of the datasheet) but in the following
instance I am stuck (probably due to my lack of understanding rather
than the datasheet.)

To do the memory bandwidth timing calculation I need to know the
following FPGA IOB timing:
1)the clock to out delay for the IOB OFF(output flipflop) and
2)setup time for the IOB IFF(input flipflop).

Finding 1) from the datasheet:
I found table 12 on page11 of the DC and switching characteristics
section. The "pin to pin clock to output time for the IOB output path"
is Tickofdcm = 2.59ns. (DCM in use) But then when I look deeper into
the datasheet I also find table 17 on pg 16 called Timing for the IOB
output path. Tiockp gives a clock to output time of 4.18ns.  What is
the difference between these two timing paramaters? What I want to
know is the time from a rising edge on OFF's OTCLK to the data bit
appearing at the FPGA Pin on the PCB.

Finding 2) from the datasheet:
Table 13 on pg 12 is called "pin to pin setup and hold times for the
IOB input path". Tpsdcm = 2.72ns is the relevant parameter.
But then table 14 "Setup and hold times for the IOB input path" show
Tiopick = 1.32ns.  Which of these two timing parameters should I use?
what is the difference?

Notes:
The IO standard used is LVCMOS25
I am using Spartan 3 datasheet DS099, march 4, 2004.

I also noticed an interesting thing in table 19, output timing
adjustments for IOB, LVCMOS25 FAST. The 16mA and 24mA drivers are
slower than the 12mA drivers? I expected them to be faster.

Also noticed the datasheet seems to be "advance product specification"
which according to the datasheet is described as "These specifications
are based on simulations only...." Scary stuff.  Is there a more
appropriate place I should be getting my timing numbers from, e.g.
download latest speed files and use timing analyzer? Is the
documentation just out of date? They must have characterized the
production silicon right?

Regards
Andrew