hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0407252155.6c7df59b@posting.google.com>...
> Hi, can anybody tell me how to get the total gate count approximation
> from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank
> you very much.


Hi Jasmine,

maybe you could have a look at a data sheet of Altera Stratix devices
where the build up of such a Logic Element is
explained. I guess there you should be able to 
find the number of gates per LE.

Rgds

Andr&#4294967295;

hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0407252155.6c7df59b@posting.google.com>...
> Hi, can anybody tell me how to get the total gate count approximation
> from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank
> you very much.

Check out AN 110: Gate Counting Methodology for APEX 20K Devices -
http://www.altera.com/literature/an/an110.pdf

LE's from APEX roughly compare to Stratix LE's if LUT's and Registers
is what you need.

K.R. Karl

Have a look at the internal macrocell structure. It is different
depending on the family. It basically is a Flipflop with some
logic in front. The compiler converts your wishes to connections.
Depending on your preference speed may be the focus or size.
The resulting connections leave some unused gates. The rough
LE-to-gatecount estimate are ballpark figures and just tell you
about the order. Make sure not to plan with an FPGA that is
too small.
You best do a design with the supplied tools and let the tool
choose a chip for your. Then have a look at the unused gates and
think about future wishes and such.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Jasmine Hau wrote:

> Hi, can anybody tell me how to get the total gate count approximation
> from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank
> you very much.

The gate count is a random number generated by marketing used to 'prove' one
FPGA is better than another.
Its usually based upon the number of and gates you can implement multiplied
by a fudge factor.



"Jasmine Hau" <hauyuanwen1980@yahoo.com> wrote in message
news:fc6016ce.0407252155.6c7df59b@posting.google.com...
> Hi, can anybody tell me how to get the total gate count approximation
> from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank
> you very much.

Hi, can anybody tell me how to get the total gate count approximation
from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank
you very much.