> On 28/7/2014 6:22 PM, already5chosen@yahoo.com wrote:
>> Multiple Nios2 cores, each with its own JTAG UART, co-exist just fine on=
the same JTAG interface. The same applies to multiple JTAG debug modules.
>> The only thing that you, as designer of the module, should care about is=
avoiding the conflict of Nios2 CPU instance IDs. Ideally, allocation of in=
stance IDs should be governed by person, that is responsible for top-level =
integration.
>
> I can't seem to debug two Nios processors simultaneously.
>
Few years ago I had system with 8 Cyclon chips and each with nios II.
All chips in single jtag chain.
I was able to debug 2 or 3 of them at same time without any problem.
There sould be not a problem to debug all 8 at once.
Adam
---
Ta wiadomo=C5=9B=C4=87 e-mail jest wolna od wirus=C3=B3w i z=C5=82o=C5=9Bli=
wego oprogramowania, poniewa=C5=BC ochrona avast! Antivirus jest aktywna.
http://www.avast.com
Reply by ●July 30, 20142014-07-30
On Wednesday, July 30, 2014 3:52:10 AM UTC+3, Ang Zhi Ping wrote:
> On 29/7/2014 10:34 PM, already5chosen@yahoo.com wrote:
>
> > On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote:
>
> >> On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote:
>
> >>
>
> >>>
>
> >>> Did you assign different instance IDs?
>
> >>
>
> >> Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE
>
> >> is able to tell the different NIOS.
>
> >>
>
> >>> I never tried to use debuggers on two Nios2 processors myself (I hate debuggers in general, so I didn't use debugger on *one* Nios2 processor for something like 7 years), but Altera documentation claims that it should work.
>
> >>
>
> >> If the JTAG UART is used for stdout, the JTAG only routes the debugging
>
> >> Nios to console. Any other Nios processors that are not being debugged
>
> >> will not be able to route their stdout outputs to console. Hence this
>
> >> question about routing messages via serial port.
>
> >>
>
> >
>
> > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies?
>
> > You should use separate JTAG UARTs for separate Nios2 cores.
>
> > Personally, I prefer not only separate JTAG UARTs, but completely separate SOPC (now known as QSYS) "systems". That way I better understand interaction of resets.
>
> Yes we only have a single JTAG port for our embedded target,
Of course, one Altera FPGA would at most have one JTAG port. That's not what I am talking about.
I am talking about multiple instances of "jtag uart" component.
> but multiple serial ports to spare.
Reply by Ang Zhi Ping●July 29, 20142014-07-29
On 29/7/2014 10:34 PM, already5chosen@yahoo.com wrote:
> On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote:
>> On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote:
>>
>>>
>>> Did you assign different instance IDs?
>>
>> Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE
>> is able to tell the different NIOS.
>>
>>> I never tried to use debuggers on two Nios2 processors myself (I hate debuggers in general, so I didn't use debugger on *one* Nios2 processor for something like 7 years), but Altera documentation claims that it should work.
>>
>> If the JTAG UART is used for stdout, the JTAG only routes the debugging
>> Nios to console. Any other Nios processors that are not being debugged
>> will not be able to route their stdout outputs to console. Hence this
>> question about routing messages via serial port.
>>
>
> You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies?
> You should use separate JTAG UARTs for separate Nios2 cores.
> Personally, I prefer not only separate JTAG UARTs, but completely separate SOPC (now known as QSYS) "systems". That way I better understand interaction of resets.
Yes we only have a single JTAG port for our embedded target, but
multiple serial ports to spare.
Reply by glen herrmannsfeldt●July 29, 20142014-07-29
rickman <gnuarm@gmail.com> wrote:
> On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote:
>> You constantly use the phrase "JTAG UART" - single, instead
>> of "JTAG UARTs" - multiple. May be, that's where your problem lies?
> I know what a UART is, I know what JTAG means, but what
> is a JTAG UART?
It does seem a strange term for it, but since JTAG is bit serial,
and most systems use bytes or some larger word, there has to be
a serial/parallel conversion somewhere along the way.
However, as I understand it, JTAG is synchronous, so that should be
USRT instead of UART.
-- glen
Reply by Theo Markettos●July 29, 20142014-07-29
rickman <gnuarm@gmail.com> wrote:
> On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote:
> >
> > You constantly use the phrase "JTAG UART" - single, instead of "JTAG
> > UARTs" - multiple. May be, that's where your problem lies?
>
> I know what a UART is, I know what JTAG means, but what is a JTAG UART?
It's a terminal-like device that grabs hold of an internal interface to
Altera's JTAG controller, with the result that you can attach a NIOS
processor (or other endpoint) to it inside the FPGA, and then run a program
called nios2-terminal on the host PC which receives the character
input/output. In other words it's a character stream multiplexed over the
host PC JTAG connection (which itself goes over TCP and then probably USB),
instead of plugging in a serial cable to the FPGA.
The actual JTAG UART isn't really very UART-like though, it's somewhat
lacking in the usual UART features.
I don't have anything major to contribute to the OP's question: I've run
multiple JTAG UARTs out of one Qsys project, and that works fine. I haven't
tried multiple NIOSes that I can recall, but these have multiple masters
driving multiple UARTs (we have some hackery to make a JTAG UART accept
Avalon streams by simulating writes to its config registers). I've also run
16 JTAG UARTs on the same JTAG chain, where each UART was on a different
FPGA. That worked, if slightly flaky due to timing issues on the very long
chain.
Theo
Reply by rickman●July 29, 20142014-07-29
On 7/29/2014 7:05 PM, already5chosen@yahoo.com wrote:
> On Wednesday, July 30, 2014 1:47:16 AM UTC+3, rickman wrote:
>> On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote:
>>
>>>
>>
>>> You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies?
>>
>> I know what a UART is, I know what JTAG means, but what is a JTAG UART?
>>
>>
>> Rick
>
> From Quartus II Handbook: "The JTAG UART is an Avalon-MM slave device that can be used in conjunction with the System Console to send and receive bytestreams."
>
> Now, if you are going to ask "What is "an Avalon-MM" and what is "the System Console" ?" then I am not going to answer.
No, lol. So this is an Altera specific term. Got it.
--
Rick
Reply by ●July 29, 20142014-07-29
On Wednesday, July 30, 2014 1:47:16 AM UTC+3, rickman wrote:
> On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote:
>
> >
>
> > You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies?
>
> I know what a UART is, I know what JTAG means, but what is a JTAG UART?
>
>
> Rick
From Quartus II Handbook: "The JTAG UART is an Avalon-MM slave device that can be used in conjunction with the System Console to send and receive bytestreams."
Now, if you are going to ask "What is "an Avalon-MM" and what is "the System Console" ?" then I am not going to answer.
Reply by rickman●July 29, 20142014-07-29
On 7/29/2014 10:34 AM, already5chosen@yahoo.com wrote:
>
> You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs" - multiple. May be, that's where your problem lies?
I know what a UART is, I know what JTAG means, but what is a JTAG UART?
--
Rick
Reply by ●July 29, 20142014-07-29
On Tuesday, July 29, 2014 5:20:53 AM UTC+3, mnentwig wrote:
> >> the topic was "light" debugging with printouts.
>
>
>
> BTW my on-board VGA controller may seem a little over-the-top . The main>
> selling point is, it doesn't slow down the code, it's an infinite-baudrate
> UART. It's surprisingly compact if I can spare one clock and a block RAM
> (on Xilinx Spartan 6, haven't tried this yet on Altera).
> Electrically it's uncritical, patch cables to a cheap RGB resistor DAC
> breakout board / "wing" work just fine at 640x480 / 25 MHz.
>
"Infinite-baudrate" is good, but difficulty of logging printouts into file is bad. For me, the later easily outweighs the former.
Reply by ●July 29, 20142014-07-29
On Tuesday, July 29, 2014 6:20:10 AM UTC+3, Ang Zhi Ping wrote:
> On 29/7/2014 4:14 AM, already5chosen@yahoo.com wrote:
>=20
> > =20
> > Did you assign different instance IDs?=20
>=20
> Yes different instance IDs are assigned. The JTAG UART under Eclipse IDE=
=20
> is able to tell the different NIOS.=20
>=20
> > I never tried to use debuggers on two Nios2 processors myself (I hate d=
ebuggers in general, so I didn't use debugger on *one* Nios2 processor for =
something like 7 years), but Altera documentation claims that it should wor=
k.=20
>=20
> If the JTAG UART is used for stdout, the JTAG only routes the debugging=
=20
> Nios to console. Any other Nios processors that are not being debugged=20
> will not be able to route their stdout outputs to console. Hence this=20
> question about routing messages via serial port.
>=20
You constantly use the phrase "JTAG UART" - single, instead of "JTAG UARTs"=
- multiple. May be, that's where your problem lies?
You should use separate JTAG UARTs for separate Nios2 cores.
Personally, I prefer not only separate JTAG UARTs, but completely separate =
SOPC (now known as QSYS) "systems". That way I better understand interactio=
n of resets.
>=20
>=20
> > I did try software download (which aso uses debugger interface) to diff=
erent Nios2 processors over the same JTAG interface. It certainly works. I =
never tested if it works simultaneously, because I never wanted to download=
simultaneously.
>=20
>=20
>=20
> The JTAG certainly work for multi-Nios system, but it cannot handle
>=20
> stdout from multiple Nios.
>=20
>=20
>=20
> > But all that is slightly off topic. The topic was "light" debugging wit=
h printouts. That's the method that I do like and do do regularly. Printout=
s over JTAG UARTs from different processor most definitely work simultaneou=
sly, there are no problems at all. Just specify correct instance ID in nios=
2-terminal command line and everything will work for you in the best possib=
le manner.
>=20
>=20
>=20
> Haha ok let's keep this thread on topic then.