I'm trying to get started with a design using a Lattice ICE40HX (done
that before) but this time I'm using the PLL. My usual design flow (with
Lattice ECP3  or XP2) is to use the Lattice IP generator to make a VHDL
entity which I drop into an Aldec HDL workspace where they happily
compile and can be simulated. (works with PLLs, RAMs, DSP etc).
The ICE40 tool makes two 'VHDL' files:
(called pll_24_48_inst.vhd and pll_24_48.vhd)

the simulator can't cope with pll_24_48.vhd, initially because I can't 
locate SB_PLL40_PAD - if anyone has ever managed to simulate the ICE40 
PLLs I'd love to know how.

For now I'm making my own simulatable PLL model but I have to be very 
careful to make it totally interchangeable with the pll_24_48.vhd which 
is what the synthesiser uses.

Michael Kellett


pll_24_48_inst: pll_24_48
port map(
           PACKAGEPIN => ,
           PLLOUTCORE => ,
           PLLOUTGLOBAL => ,
           RESET => ,
           LOCK =>
         );


and

library IEEE;
use IEEE.std_logic_1164.all;

entity pll_24_48 is
port(
       PACKAGEPIN: in std_logic;
       RESET: in std_logic;
       PLLOUTCORE: out std_logic;
       PLLOUTGLOBAL: out std_logic;
       LOCK: out std_logic
     );
end entity pll_24_48;

architecture BEHAVIOR of pll_24_48 is
component SB_PLL40_PAD
   generic (
        		--- Feedback
		FEEDBACK_PATH	 		 : string := "SIMPLE"; -- String (simple, delay,
phase_and_delay, external)
		DELAY_ADJUSTMENT_MODE_FEEDBACK 	 : string := "FIXED";
		DELAY_ADJUSTMENT_MODE_RELATIVE 	 : string := "FIXED";
		SHIFTREG_DIV_MODE 		: bit_vector(1 downto 0)	:= "00"; 	 --  0-->Divide
by 4, 1-->Divide by 7, 3 -->Divide by 5	
	  	FDA_FEEDBACK 			: bit_vector(3 downto 0) 	:= "0000"; 	 --  Integer
(0-15).
		FDA_RELATIVE 			: bit_vector(3 downto 0)	:= "0000"; 	 --  Integer (0-15).
		PLLOUT_SELECT			: string := "GENCLK";

   		--- Use the spread sheet to populate the values below
		DIVF				: bit_vector(6 downto 0);  -- Determine a good default value
		DIVR				: bit_vector(3 downto 0);  -- Determine a good default value
		DIVQ				: bit_vector(2 downto 0);  -- Determine a good default value
		FILTER_RANGE			: bit_vector(2 downto 0);  -- Determine a good default
value

   		--- Additional C-Bits
   		ENABLE_ICEGATE			: bit := '0';

   		--- Test Mode Parameter
		TEST_MODE			: bit := '0';
		EXTERNAL_DIVIDE_FACTOR		: integer := 1 -- Not Used by model, Added for
PLL config GUI
        );
   port (
         PACKAGEPIN		: inout std_logic;
         PLLOUTCORE		: out std_logic;		    -- PLL output to core logic
         PLLOUTGLOBAL		: out std_logic;		    -- PLL output to global network
         EXTFEEDBACK		: in std_logic;			    -- Driven by core logic
         DYNAMICDELAY		: in std_logic_vector (7 downto 0); -- Driven by
core logic
         LOCK				: out std_logic;	 	    -- Output of PLL
         BYPASS			: in std_logic;			    -- Driven by core logic
         RESETB			: in std_logic;			    -- Driven by core logic
         LATCHINPUTVALUE		: in std_logic;			    -- iCEGate Signal
         -- Test Pins
         SDO			: out std_logic;				-- Output of PLL
         SDI			: in std_logic;					-- Driven by core logic
         SCLK			: in std_logic					-- Driven by core logic
        );
end component;
begin
pll_24_48_inst: SB_PLL40_PAD
-- Fin=24, Fout=48
generic map(
              DIVR => "0000",
              DIVF => "0011111",
              DIVQ => "100",
              FILTER_RANGE => "010",
              FEEDBACK_PATH => "SIMPLE",
              DELAY_ADJUSTMENT_MODE_FEEDBACK => "FIXED",
              FDA_FEEDBACK => "0000",
              DELAY_ADJUSTMENT_MODE_RELATIVE => "FIXED",
              FDA_RELATIVE => "0000",
              SHIFTREG_DIV_MODE => "00",
              PLLOUT_SELECT => "GENCLK",
              ENABLE_ICEGATE => '0'
            )
port map(
           PACKAGEPIN => PACKAGEPIN,
           PLLOUTCORE => PLLOUTCORE,
           PLLOUTGLOBAL => PLLOUTGLOBAL,
           EXTFEEDBACK => open,
           DYNAMICDELAY => open,
           RESETB => RESET,
           BYPASS => '0',
           LATCHINPUTVALUE => open,
           LOCK => LOCK,
           SDI => open,
           SDO => open,
           SCLK => open
         );

end BEHAVIOR;