Looks like the main improvement over VirtexIIpro is the reduction in time to
get on and off the carry chain. Tbyp is 88ps = 44ps/bit in the slowest
VIIpro. But the time on and off the chain, e.g. Topcyf is about twice as
quick in the V4, saving c.400ps meaning you get more than 16 bits longer a
counter at the same speed.
Cheers, Syms.
"Philip Freidin" <philip@fliptronics.com> wrote in message
news:ib5ij056k378e2m6ot9kc75gr2cr9nkmt0@4ax.com...
>
>
> Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary
> speed files. Gotta love the 41.5 ps/bit carry chain.
>
>>
> Philip
>
> Philip Freidin
> Fliptronics
Reply by Ray Andraka●September 9, 20042004-09-09
Philip,
If you get a chance, play with the DSP blocks. The speeds in there are much
more impressive than the speeds of the fabric.
Philip Freidin wrote:
> Well,
> Xilinx shipped me my Foundation 6.3i software update,
> and since it has the initial support for Virtex 4,
> I installed it and did a design.
>
> Here it is:
>
> ====
>
> module top(in_bus,out_bus);
> input [15:0] in_bus;
> output [15:0] out_bus;
>
> assign out_bus = {in_bus[14:0],in_bus[15]};
>
> endmodule
>
> ====
>
> Par Report (trimmed):
>
> Release 6.3i Par G.35
> Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
> Thu Sep 02 19:16:08 2004
> Loading device database for application Par from file "top_map.ncd".
> "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
> Loading device for application Par from file '4vfx12.nph' in environment
> Device speed data version: PREVIEW 1.46 2004-07-09.
> Device utilization summary:
> Number of External IOBs 32 out of 240 13%
> Number of LOCed External IOBs 0 out of 32 0%
>
> Total REAL time to PAR completion: 19 secs
> Total CPU time to PAR completion: 18 secs
>
> Peak Memory Usage: 105 MB
>
> Placement: Completed - No errors found.
> Routing: Completed - No errors found.
>
> ====
>
> Some of the manuals are single page PDFs, that point you to
> the web site to get the real thing.
>
> Although you all do HDL designs only, you might want to get
> the Schematic Designers library guide as well as the HDL guide,
> as the HDL one is 290 pages, and the schematic one is 700 pages.
> Most of the extra stuff is stuff you don't need, such as 4 bit
> counter macros, but there are also some things that are pretty
> interesting that seem to have been left out of the HDL version.
> Probably fixed in the next version.
>
> FPGA editor shows lots of interesting new stuff. Still waiting
> for a data sheet, as the FPGA editor shows you details of the
> forest from the perspective of having your nose pressed against
> a huge tree :-) and the library guides is mostly very detailed
> for simple stuff like logic and FF primitives, and not nearly
> as much info as you might want for the complex stuff.
>
> If this is the sort of thing you like, then you will probably
> like this sort of thing.
>
> Philip
>
> Philip Freidin
> Fliptronics
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Reply by Philip Freidin●September 3, 20042004-09-03
On Fri, 03 Sep 2004 17:52:50 +1200, Jim Granville <no.spam@designtools.co.nz> wrote:
> Wot, No Speed reports ?
>You should try a 32 bit ctr, and see what it reports :)
>-jg
Sure, with an input register and output register to isolate the
counter performance from the I/O performance.
Set clock period goal to 250 MHz.
====
module top(in_bus,out_bus,clock);
input [31:0] in_bus;
output [31:0] out_bus;
input clock;
reg [31:0] counter;
reg [31:0] in_bus_reg;
reg [31:0] out_bus_reg;
always @(posedge clock) begin
counter <= counter + 1;
out_bus_reg <= counter | in_bus_reg;
in_bus_reg <= in_bus;
end
assign out_bus = out_bus_reg;
endmodule
====
Trimmed PAR report:
Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Fri Sep 03 19:03:36 2004
E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf
Loading device database for application Par from file "top_map.ncd".
"top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
Loading device for application Par from file '4vfx12.nph' in environment
E:/Xilinx.
Device speed data version: PREVIEW 1.46 2004-07-09.
Device utilization summary:
Number of External IOBs 65 out of 240 27%
Number of LOCed External IOBs 0 out of 65 0%
Number of ILOGICs 32 out of 320 10%
Number of OLOGICs 32 out of 320 10%
Number of Slices 16 out of 5472 1%
Number of BUFGs 1 out of 32 3%
Overall effort level (-ol): High (set by user)
Placer effort level (-pl): High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): High (set by user)
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
+-------------------------+----------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
| clock_BUFGP |BUFGCTRL_X| No | 80 | 0.433 | 1.655 |
+-------------------------+----------+------+------+------------+-------------+
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
TS_clock = PERIOD TIMEGRP "clock" 4 nS | 4.000ns | 3.673ns | 0
HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
OFFSET = IN 10 nS BEFORE COMP "clock" | 10.000ns | 5.562ns | 2
--------------------------------------------------------------------------------
OFFSET = OUT 10 nS AFTER COMP "clock" | 10.000ns | 6.316ns | 1
--------------------------------------------------------------------------------
Total REAL time to PAR completion: 1 mins 9 secs
Total CPU time to PAR completion: 1 mins 9 secs
Peak Memory Usage: 142 MB
Timing report:
(selected pieces)
================================================================================
Timing constraint: TS_clock = PERIOD TIMEGRP "clock" 4 nS HIGH 50.000000 % ;
592 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 3.673ns.
--------------------------------------------------------------------------------
Slack: 0.327ns (requirement - (data path - clock path skew + uncertainty))
Source: counter_10 (FF)
Destination: out_bus_reg_10 (FF)
Requirement: 4.000ns
Data Path Delay: 3.673ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: clock_BUFGP rising at 0.000ns
Destination Clock: clock_BUFGP rising at 4.000ns
Clock Uncertainty: 0.000ns
Data Path: counter_10 to out_bus_reg_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y75.XQ Tcko 0.290 counter<10>
counter_10
OLOGIC_X0Y74.SR net (fanout=2) 2.604 counter<10>
OLOGIC_X0Y74.CLK Tosrck 0.779 out_bus_reg<10>
out_bus_reg_10
------------------------------------------------- ---------------------------
Total 3.673ns (1.069ns logic, 2.604ns route)
(29.1% logic, 70.9% route)
--------------------------------------------------------------------------------
Slack: 1.254ns (requirement - (data path - clock path skew + uncertainty))
Source: counter_1 (FF)
Destination: counter_31 (FF)
Requirement: 4.000ns
Data Path Delay: 2.741ns (Levels of Logic = 16)
Clock Path Skew: -0.005ns
Source Clock: clock_BUFGP rising at 0.000ns
Destination Clock: clock_BUFGP rising at 4.000ns
Clock Uncertainty: 0.000ns
Data Path: counter_1 to counter_31
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y70.YQ Tcko 0.290 counter<0>
counter_1
SLICE_X47Y70.G3 net (fanout=2) 0.364 counter<1>
SLICE_X47Y70.COUT Topcyg 0.476 counter<0>
counter<1>_rt
counter_LPM_COUNTER_1__n0000<1>cy
SLICE_X47Y71.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<1>_cyo
SLICE_X47Y71.COUT Tbyp 0.083 counter<2>
counter_LPM_COUNTER_1__n0000<2>cy
counter_LPM_COUNTER_1__n0000<3>cy
SLICE_X47Y72.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<3>_cyo
SLICE_X47Y72.COUT Tbyp 0.083 counter<4>
counter_LPM_COUNTER_1__n0000<4>cy
counter_LPM_COUNTER_1__n0000<5>cy
SLICE_X47Y73.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<5>_cyo
SLICE_X47Y73.COUT Tbyp 0.083 counter<6>
counter_LPM_COUNTER_1__n0000<6>cy
counter_LPM_COUNTER_1__n0000<7>cy
SLICE_X47Y74.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<7>_cyo
SLICE_X47Y74.COUT Tbyp 0.083 counter<8>
counter_LPM_COUNTER_1__n0000<8>cy
counter_LPM_COUNTER_1__n0000<9>cy
SLICE_X47Y75.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<9>_cyo
SLICE_X47Y75.COUT Tbyp 0.083 counter<10>
counter_LPM_COUNTER_1__n0000<10>cy
counter_LPM_COUNTER_1__n0000<11>cy
SLICE_X47Y76.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<11>_cyo
SLICE_X47Y76.COUT Tbyp 0.083 counter<12>
counter_LPM_COUNTER_1__n0000<12>cy
counter_LPM_COUNTER_1__n0000<13>cy
SLICE_X47Y77.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<13>_cyo
SLICE_X47Y77.COUT Tbyp 0.083 counter<14>
counter_LPM_COUNTER_1__n0000<14>cy
counter_LPM_COUNTER_1__n0000<15>cy
SLICE_X47Y78.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<15>_cyo
SLICE_X47Y78.COUT Tbyp 0.083 counter<16>
counter_LPM_COUNTER_1__n0000<16>cy
counter_LPM_COUNTER_1__n0000<17>cy
SLICE_X47Y79.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<17>_cyo
SLICE_X47Y79.COUT Tbyp 0.083 counter<18>
counter_LPM_COUNTER_1__n0000<18>cy
counter_LPM_COUNTER_1__n0000<19>cy
SLICE_X47Y80.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<19>_cyo
SLICE_X47Y80.COUT Tbyp 0.083 counter<20>
counter_LPM_COUNTER_1__n0000<20>cy
counter_LPM_COUNTER_1__n0000<21>cy
SLICE_X47Y81.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<21>_cyo
SLICE_X47Y81.COUT Tbyp 0.083 counter<22>
counter_LPM_COUNTER_1__n0000<22>cy
counter_LPM_COUNTER_1__n0000<23>cy
SLICE_X47Y82.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<23>_cyo
SLICE_X47Y82.COUT Tbyp 0.083 counter<24>
counter_LPM_COUNTER_1__n0000<24>cy
counter_LPM_COUNTER_1__n0000<25>cy
SLICE_X47Y83.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<25>_cyo
SLICE_X47Y83.COUT Tbyp 0.083 counter<26>
counter_LPM_COUNTER_1__n0000<26>cy
counter_LPM_COUNTER_1__n0000<27>cy
SLICE_X47Y84.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<27>_cyo
SLICE_X47Y84.COUT Tbyp 0.083 counter<28>
counter_LPM_COUNTER_1__n0000<28>cy
counter_LPM_COUNTER_1__n0000<29>cy
SLICE_X47Y85.CIN net (fanout=1) 0.000 counter_LPM_COUNTER_1__n0000<29>_cyo
SLICE_X47Y85.CLK Tcinck 0.449 counter<30>
counter_LPM_COUNTER_1__n0000<30>cy
counter_LPM_COUNTER_1__n0000<31>_xor
counter_31
------------------------------------------------- ---------------------------
Total 2.741ns (2.377ns logic, 0.364ns route)
(86.7% logic, 13.3% route)
Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary
speed files. Gotta love the 41.5 ps/bit carry chain.
On 03 Sep 2004 15:40:35 -0700, in comp.arch.fpga Eric Smith wrote:
>Philip Freidin <philip@fliptronics.com> writes:
>> Some of the manuals are single page PDFs, that point you to
>> the web site to get the real thing.
>
>Ugh! I always hate that sort of thing. CDs are cheap, they should
>include the real docs. (It's all well and good to suggest looking at
>the web site for updates.)
This is clearly not a CD issue. Most of the manuals are included.
The ones that were stubbed, are the ones that were obviously not
ready at the time they had everything else ready to commit to CD.
These are basically the Virtex-4 library guides.
You can get them here:
http://www.xilinx.com/support/sw_manuals/xilinx6/download/
>What happens in five years when a customer needs you to revise an
>old design? You discover that Foundation ISE 11.2 doesn't support
>the old parts, or that for some reason the old design doesn't build
>right with it, so you get out your old CD of ISE 6.3. And then
>discover that you don't have the actual documentation.
> Some of the manuals are single page PDFs, that point you to
> the web site to get the real thing.
Ugh! I always hate that sort of thing. CDs are cheap, they should
include the real docs. (It's all well and good to suggest looking at
the web site for updates.)
What happens in five years when a customer needs you to revise an
old design? You discover that Foundation ISE 11.2 doesn't support
the old parts, or that for some reason the old design doesn't build
right with it, so you get out your old CD of ISE 6.3. And then
discover that you don't have the actual documentation.
Years ago people told me that as more and more information became
available digitally, particular works would be available on a permanent
basis, because storage capacity and bandwidth keep increasing, and
there's no longer an reason why things should go out of print. The
publisher doesn't have to keep a warehouse of books that only sell a
copy occasionally; instead it is just bits on a hard drive.
While there may be some small amount of truth to that, the reality is
that most digital works are even more ephemeral than the paper they are
replacing.
Sigh.
Reply by Jim Granville●September 3, 20042004-09-03
Philip Freidin wrote:
> Well,
> Xilinx shipped me my Foundation 6.3i software update,
> and since it has the initial support for Virtex 4,
> I installed it and did a design.
<snip>
> Par Report (trimmed):
>
> Release 6.3i Par G.35
> Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
> Thu Sep 02 19:16:08 2004
> Loading device database for application Par from file "top_map.ncd".
> "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
> Loading device for application Par from file '4vfx12.nph' in environment
> Device speed data version: PREVIEW 1.46 2004-07-09.
> Device utilization summary:
> Number of External IOBs 32 out of 240 13%
> Number of LOCed External IOBs 0 out of 32 0%
Wot, No Speed reports ?
You should try a 32 bit ctr, and see what it reports :)
-jg
Reply by Philip Freidin●September 3, 20042004-09-03
Well,
Xilinx shipped me my Foundation 6.3i software update,
and since it has the initial support for Virtex 4,
I installed it and did a design.
Here it is:
====
module top(in_bus,out_bus);
input [15:0] in_bus;
output [15:0] out_bus;
assign out_bus = {in_bus[14:0],in_bus[15]};
endmodule
====
Par Report (trimmed):
Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Thu Sep 02 19:16:08 2004
Loading device database for application Par from file "top_map.ncd".
"top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
Loading device for application Par from file '4vfx12.nph' in environment
Device speed data version: PREVIEW 1.46 2004-07-09.
Device utilization summary:
Number of External IOBs 32 out of 240 13%
Number of LOCed External IOBs 0 out of 32 0%
Total REAL time to PAR completion: 19 secs
Total CPU time to PAR completion: 18 secs
Peak Memory Usage: 105 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
====
Some of the manuals are single page PDFs, that point you to
the web site to get the real thing.
Although you all do HDL designs only, you might want to get
the Schematic Designers library guide as well as the HDL guide,
as the HDL one is 290 pages, and the schematic one is 700 pages.
Most of the extra stuff is stuff you don't need, such as 4 bit
counter macros, but there are also some things that are pretty
interesting that seem to have been left out of the HDL version.
Probably fixed in the next version.
FPGA editor shows lots of interesting new stuff. Still waiting
for a data sheet, as the FPGA editor shows you details of the
forest from the perspective of having your nose pressed against
a huge tree :-) and the library guides is mostly very detailed
for simple stuff like logic and FF primitives, and not nearly
as much info as you might want for the complex stuff.
If this is the sort of thing you like, then you will probably
like this sort of thing.
Philip
Philip Freidin
Fliptronics