Victor Schutte wrote:

>Adding 800ns is quite heavy, possibly done with a counter 800ns/ 20ns period
>after which the signal is asserted. The same can be done for 80ns (only 4
>periods).
>
>The compilers are usually intelligent when it comes to optimizing. You add
>more time wasting gates and it removes it to increase speed. The one option
>is to route a signal to a pin and back through another but that is usually
>ineffective and ugly, and ony adds a few ns to the signal.
>  
>
I used a version of this in a CPLD application where there was no continuous
frequency clock.  I put a 5.1 K resistor between an output pin and an input
pin, using the parasitic capacitance of the input pin as the C for the 
RC delay.
This worked quite well to clock a counter after the removal of a bus strobe
signal.  I doubt you could make this work reliably for 800 ns, but 80 ns 
might
be doable.  For 800 ns, assuming you don't have enough CLBs for the 
requisite
counter, you would need an external one shot or counter.

>  
>
Jon

Adding 800ns is quite heavy, possibly done with a counter 800ns/ 20ns period
after which the signal is asserted. The same can be done for 80ns (only 4
periods).

The compilers are usually intelligent when it comes to optimizing. You add
more time wasting gates and it removes it to increase speed. The one option
is to route a signal to a pin and back through another but that is usually
ineffective and ugly, and ony adds a few ns to the signal.

My suggestion is to create a small counter and count 4 x 20ns periods for
80ns (or 40 x 20ns periods for 800ns) before asserting the signal. At these
slow speeds you can also consider a simple state machine to handle the  I/O.

Victor Schutte
victor@zertec.co.za

http://www.zertec.co.za


"Paul Gray" <agarvey@kimble.ie> wrote in message
news:263cf391.0409140237.5b966c4e@posting.google.com...
> I need to delay one of the output signals from my cpld by 80nS.
> The clock frequency of our board is 48MHz.
>
> Im using the altera quartus software.
>
> We have data and address lines and a chip select going into the cpld.
> The outputs are open drain. When the data and address lines are
> changed from a Low to a High state they take about 60ns to rise up on
> the ouputs of the CPLD.
>
> The problem is the chip select line is active low and drops from a
> high to a low almost instantaneous. So things aren't lining up.
>
> I was able to move the chip select drop to a low by adding in LCELL's.
> This delayed the chip select until the data and address lines are set
> up on the outputs.
>
> The problem now is that the chip select line is now moved along and
> does not return high before the data and address lines change.
>
> i am trying to set the chip select back high after a set amount of
> time but the software does not seem to be registering the TIMING in
> the VHDL code.
>
> For example, in my open drain code i am trying to reset the output of
> the chip select high but it is not happening.
>
> temp <= A;
>
> process(temp)
> begin
> if temp = '1' then
> Y <= 'Z';
> else
> Y <= '0', 'Z' after 800ns;
>
> end if;
>
> end process;
>
> end cont;
>
>
> i would b grateful for any help
> paul

On 14 Sep 2004 03:37:01 -0700, agarvey@kimble.ie (Paul Gray) wrote:
>i am trying to set the chip select back high after a set amount of
>time but the software does not seem to be registering the TIMING in
>the VHDL code.
>
>For example, in my open drain code i am trying to reset the output of
>the chip select high but it is not happening.
>
>temp <= A;
>
>process(temp)
>begin
>	if temp = '1' then
>		Y <= 'Z';
>	else 
>		Y <= '0', 'Z' after 800ns;
>	
>	end if;
>	
>end process;
>
>end cont;
>
>
>i would b grateful for any help
>paul


Hi Paul,

From your question, I am guessing you are new to VHDL, new to CPLDs,
and probably new to digital design.

While you could be given a straight answer to your question, I think
you would be better served with advice on what you should do to learn
why you aren't getting the results you want.

The first thing I would recommend is to read the data sheet for the
CPLD, and in particular, the resources that the CPLD has. No matter
what you write in VHDL, the chip only has a fixed number of specific
resources. So if you write "after 800ns" you need to look at the CPLD
resources, and see what it has that may be able to do this. If you can't
find such a resource, then it is unlikely that the VHDL could somehow
magically change what is available in the CPLD.

Second, You should read some introductory text on VHDL, and in particular,
note that it is really two languages. There is the full language that is
designed for simulation, and there is a subset language, for synthesis.
Since you are trying to create a design for a CPLD, you must restrict
your self to the synthesis subset for the design part of your project.
For the simuation part of your project, you can create a test bench
wrapper that can use the full language.
You will find that the synthesis subset does not support "after 800ns"

Third, the use of open drain busses is highly unusual for address
and data in current design practice (mini computers of 30 years ago
did this for their backplane busses). Current designs typically use
a tristate bus, that can actively drive high and low for the duration
of a transaction, and thus you would not see the resitive pull up
problems you are experiencing.

Good luck,
Philip







===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM

I need to delay one of the output signals from my cpld by 80nS.
The clock frequency of our board is 48MHz.

Im using the altera quartus software.

We have data and address lines and a chip select going into the cpld.
The outputs are open drain. When the data and address lines are
changed from a Low to a High state they take about 60ns to rise up on
the ouputs of the CPLD.

The problem is the chip select line is active low and drops from a
high to a low almost instantaneous. So things aren't lining up.

I was able to move the chip select drop to a low by adding in LCELL's.
This delayed the chip select until the data and address lines are set
up on the outputs.

The problem now is that the chip select line is now moved along and
does not return high before the data and address lines change.

i am trying to set the chip select back high after a set amount of
time but the software does not seem to be registering the TIMING in
the VHDL code.

For example, in my open drain code i am trying to reset the output of
the chip select high but it is not happening.

temp <= A;

process(temp)
begin
	if temp = '1' then
		Y <= 'Z';
	else 
		Y <= '0', 'Z' after 800ns;
	
	end if;
	
end process;

end cont;


i would b grateful for any help
paul