"Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message
news:41493704.2050000@DELETEALLCAPSamontec.com...
> Antti Lukats wrote:
> > "Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in
message
> > news:414838f8$1@news.vsnet.ch...
> >
> >>Hi all,
> >>
> >>Can I insert my own IP core in the Xilinx Core Gen?
> >>Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
> >>If not, why Xilinx does not allow that feature.
> >>
> >>Larry,
> >>www.amontec.com
> >
> >
> > yes you can.
> >
> > well there are some problems and I guess not all the core gen funtions
are
> > accesible to regular non privileged users, but you can create your own
> > coregen cores
> >
> > Antti
> >
> >
>
> Hi Antti,
>
> ... and how to do that ?
> I am searching in xilinx doc, but found nothing usable.
>
> Regards,
> Laurent
> www.amontec.com

we have done that, and the info is available too :)
http://ebook.openchip.org/IP_CorePackaging.html

Antti

Antti Lukats wrote:
> "Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message
> news:414838f8$1@news.vsnet.ch...
> 
>>Hi all,
>>
>>Can I insert my own IP core in the Xilinx Core Gen?
>>Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
>>If not, why Xilinx does not allow that feature.
>>
>>Larry,
>>www.amontec.com
> 
> 
> yes you can.
> 
> well there are some problems and I guess not all the core gen funtions are
> accesible to regular non privileged users, but you can create your own
> coregen cores
> 
> Antti
> 
> 

Hi Antti,

... and how to do that ?
I am searching in xilinx doc, but found nothing usable.

Regards,
Laurent
www.amontec.com

"Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message
news:414838f8$1@news.vsnet.ch...
> Hi all,
>
> Can I insert my own IP core in the Xilinx Core Gen?
> Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
> If not, why Xilinx does not allow that feature.
>
> Larry,
> www.amontec.com

yes you can.

well there are some problems and I guess not all the core gen funtions are
accesible to regular non privileged users, but you can create your own
coregen cores

Antti

Hi all,

Can I insert my own IP core in the Xilinx Core Gen?
Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
If not, why Xilinx does not allow that feature.

Larry,
www.amontec.com