In article <3f49ff11-d6b9-4772-b626-ff6e87ecf04b@googlegroups.com>,
Svenn Are Bjerkem  <svenn.bjerkem@gmail.com> wrote:
>Hi,
>has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe 
>endpoint interface with data as if it was inserted into a host PCIe slot.
>
>I need some pointers to documents or code describing what I have to do
>to make a simplem memory read and memory write.

Svenn,

There's multiple ways to tackle this.  Since this is an FPGA group,
one assumes you're implementing this on an FPGA.  Xilinx for example
will generate some sort of example design which you can run in your
favorite simulator, and watch your TLP packets pass by.  Hack at it
and recode as you see fit.

Normally, if your implementing an PCIE endpoint within and FPGA,
the generated example will just insert an equivalent root complex
inside the testbench to manage the low-level PCIE negotiations, etc.

Other options include purchasing PCIE verification IP from a vendor.
There's many options here. 

Other options include writing your own PCIE TLP source/sync models (at perhaps
a higher level), and tying that up in your testbench.

There's many options here to explore, all depending on your requirements.

Good luck.

--Mark

Hi,
has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe endpoint interface with data as if it was inserted into a host PCIe slot.

I need some pointers to documents or code describing what I have to do to make a simplem memory read and memory write.

-- 
Svenn