Reply by H. Peter Anvin●September 30, 20042004-09-30
Followup to: <48eaa469.0409291100.3ae7062a@posting.google.com>
By author: cyd@spectrum.montana.edu (Cy Drollinger)
In newsgroup: comp.arch.fpga
>
> I am interested in the compatibility of a VHDL project instantiating a
> verilog open core, floating point arthmetic block. Is this possible
> and if it is not is there another way to use a verilog open core
> inside a VHDL project, a transform of some kind?
>
It depends on your software. Both Xilinx ISE and Altera Quartus
support it just fine, but if you're using other tools it's up to each
tool.
-hpa
Reply by Cy Drollinger●September 29, 20042004-09-29
I am interested in the compatibility of a VHDL project instantiating a
verilog open core, floating point arthmetic block. Is this possible
and if it is not is there another way to use a verilog open core
inside a VHDL project, a transform of some kind?