ISE version 6.1i supports mixed language flows.  ISE Foundation is 
available now.  ISE WebPACK will
be ready by the end of this month.

Valentin Tihomirov wrote:

>My system has netlist in EDIF while some of technology elements used in the
>netlist are
>described in a separate VHDL file at logic level. WebPack supports only pure
>EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a
>mixed design?
>That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL
>components.
>
>May be ISE Foundation supports this?
>
>
>  
>

My system has netlist in EDIF while some of technology elements used in the
netlist are
described in a separate VHDL file at logic level. WebPack supports only pure
EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a
mixed design?
That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL
components.

May be ISE Foundation supports this?