> Hello,
>
> I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i.
>
> I am observing a illogical problem.
>
> All my flip flops are negative edge triggered but some how even if the
> edge on the clock comes cpld doesnt recognize it.
I think you might want to use the global clock pin(s) as your clock input.
VAX< 9000
>
> So I made a simple flip flop where at Power On Reset I am clearing it
> and at the edge of the clock I am setting it to 1.
>
> Even then I was not able to see that test signal as 1.
>
> When I converted the test flip flop from -ve edge to +ve edge I was
> getting proper result.
>
> After that I converted all other signals to +ve edge triggered and I
> observed same problem as was in -ve edge trigerred.even in test Flip
> Flop.
>
> Again I converted just the Test flip flop to -ve edge and kept all
> other +ve edge and again proper results.
>
> Now I want to buffer the clock as I think this is a problem of loading
> of clock.
>
> but as if I write
>
> Clock1 <= Clock;
>
> xst removes it so how can I tell xst to not remove that.
> any other suggestions for problem I m observing.
>
> Thank u
> Naimesh
Reply by ●November 5, 20042004-11-05
Naimesh wrote:
> Hello,
>
> I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i.
>
> I am observing a illogical problem.
>
> All my flip flops are negative edge triggered but some how even if the
> edge on the clock comes cpld doesnt recognize it.
>
> So I made a simple flip flop where at Power On Reset I am clearing it
> and at the edge of the clock I am setting it to 1.
>
> Even then I was not able to see that test signal as 1.
>
> When I converted the test flip flop from -ve edge to +ve edge I was
> getting proper result.
>
> After that I converted all other signals to +ve edge triggered and I
> observed same problem as was in -ve edge trigerred.even in test Flip
> Flop.
>
> Again I converted just the Test flip flop to -ve edge and kept all
> other +ve edge and again proper results.
>
> Now I want to buffer the clock as I think this is a problem of loading
> of clock.
>
> but as if I write
>
> Clock1 <= Clock;
>
> xst removes it so how can I tell xst to not remove that.
> any other suggestions for problem I m observing.
You might write
Clock1: out std_logic;
Clock: in std_loigc;
New_clock: in std_logic;
...
Clock1 <= not (clock);
...
then use New_clock to drive your Flip-flops, and connect Clock1 to New_clock
on your development board.
VAX, 9000
>
> Thank u
> Naimesh
Reply by Naimesh●November 5, 20042004-11-05
Hello,
I am doing a project in Xilinx CPLD XC9572 usign Xilix ISE 6.2i.
I am observing a illogical problem.
All my flip flops are negative edge triggered but some how even if the
edge on the clock comes cpld doesnt recognize it.
So I made a simple flip flop where at Power On Reset I am clearing it
and at the edge of the clock I am setting it to 1.
Even then I was not able to see that test signal as 1.
When I converted the test flip flop from -ve edge to +ve edge I was
getting proper result.
After that I converted all other signals to +ve edge triggered and I
observed same problem as was in -ve edge trigerred.even in test Flip
Flop.
Again I converted just the Test flip flop to -ve edge and kept all
other +ve edge and again proper results.
Now I want to buffer the clock as I think this is a problem of loading
of clock.
but as if I write
Clock1 <= Clock;
xst removes it so how can I tell xst to not remove that.
any other suggestions for problem I m observing.
Thank u
Naimesh