"Victor Schutte" <victors@mweb.co.za> wrote in message news:<cojo15$edj$1@ctb-nnrp2.saix.net>...
> The CS8900 is a rather slow chip. I am running several applications at 60MHz
> at which the chip does not operate well. Edit the class.ptf file and
> increase the wait states and setup/hold times. Then add the component and
> recompile.
In addition to Victor's advice:
If you are using a modern (Quartus II 4.1 or later) version of our
tools, SOPC Builder has the capability to dynamically calculate
peripheral latency/wait states/tsu/th. Instead of specifying an
integer as below ("5" for example), specify an integer with unit time
(for example "50ns"). SOPC Builder will interpret the time in
nanoseconds and calculate the number of clocks based on your desried
system clock frequency... that way you can read timing parameters out
of the data sheet and apply them to your peripheral.
> "vladimir" <vboykov@yandex.ru> wrote in message
> news:d6aed45c.0411301115.d80a628@posting.google.com...
> > I've made a board with CS8900 for proto of NIOS Development kit board.
> > It works very strange, I read internal registers and sometimes they
> > was read correctly but in generaly incorrectly. Writing is correctly
> > as seem to me.
> > I'm using core of SOPC. Maybe someone gives me some advise.
> > Thx.
About the problem Vladamir is seeing: It is difficult to say without
more information about your system. Victor's timing advice is an
excellent place to start. After ensuring that timing requirements are
met and that signal integrity on your board is okay (FPGA IO to
CS8900). I think the next step would be to do basic register tests as
you seem to be performing, either with a C program or the legacy GERMS
monitor... if the above doesn't work it is time to get out a scope and
see how the signals Nios is presenting to the external device look.
A side note: I am submitting a bug report to request that we update
the cs8900 component's timing to use the above convention, even though
we are no longer shipping with it in the product.
Jesse Kempa
Altera Corp.
jkempa at altera dot com
Reply by Victor Schutte●December 1, 20042004-12-01
The CS8900 is a rather slow chip. I am running several applications at 60MHz
at which the chip does not operate well. Edit the class.ptf file and
increase the wait states and setup/hold times. Then add the component and
recompile.
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "5"; ******* increase ?
Write_Wait_States = "5"; ******* increase ?
Setup_Time = "1"; ******* increase ?
Hold_Time = "1"; ******* increase ?
Is_Memory_Device = "0";
Date_Modified = "2001.10.9.10:51:51";
IRQ_Number = "--unknown--";
Base_Address = "--unknown--";
Tri_State_Data_Bus = "--unknown--";
}
Victor Schutte
http://www.zertec.co.za
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"vladimir" <vboykov@yandex.ru> wrote in message
news:d6aed45c.0411301115.d80a628@posting.google.com...
> I've made a board with CS8900 for proto of NIOS Development kit board.
> It works very strange, I read internal registers and sometimes they
> was read correctly but in generaly incorrectly. Writing is correctly
> as seem to me.
> I'm using core of SOPC. Maybe someone gives me some advise.
> Thx.
Reply by vladimir●November 30, 20042004-11-30
I've made a board with CS8900 for proto of NIOS Development kit board.
It works very strange, I read internal registers and sometimes they
was read correctly but in generaly incorrectly. Writing is correctly
as seem to me.
I'm using core of SOPC. Maybe someone gives me some advise.
Thx.