Thanks to the responses.  I'm gonna have a go at it on my own first and see
what I come up with.

Adam wrote:
> Hello all,
>
>   Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded
signal?
> I'm trying to build an SPDIF receiver and am wondering if its
possible to
> directly connect the input signal(after analog level adjustment) to
an FPGA
> ...
A Manhester decoder can be implemented in less than one Virtex-II CLB.
You need an 8x oversampling clock, but the tolerances are quite
generous:
The clock frequency must be between 5 and 12 times the incoming bit
rate.
Send me an e-mail if you need the code.
I described the concept years ago in our XCell magazine.
http://query.xilinx.com/ui/jsp/xilinx_template.jsp?field=%2Fcompany%2Fsearch.
Peter Alfke, Xilinx Applications   ( peter@xilinx.com)

A Manhester decoder can be implemented in less than one Virtex-II CLB.
You need an 8x oversampling clock, but the tolerances are quite
generous:
The clock frequency must be between 5 and 12 times the incoming bit
rate.
Send me an e-mail if you need the code.
I described the concept years ago in our XCell magazine.
http://query.xilinx.com/ui/jsp/xilinx_template.jsp?field=%2Fcompany%2Fsearch.
Peter Alfke, Xilinx Applications   ( peter@xilinx.com)

Adam wrote:

> I'm trying to build an SPDIF receiver and am wondering if its
possible to
> directly connect the input signal(after analog level adjustment) to
an FPGA
> and read the level at the 90 and 270 degree phases.

SPDIF is only 48kHz * 32 bits * 2 channels * 2 for biphase = 6MHz
Any modern FPGA will do 100MHz easy.
So just oversample the signal and decode it like a UART would.

To build a transmitter locked to the receiver would be more difficult.
Alan Nishioka
alann@accom.com

Adam wrote:

> I'm trying to build an SPDIF receiver and am wondering if its
possible to
> directly connect the input signal(after analog level adjustment) to
an FPGA
> and read the level at the 90 and 270 degree phases.

SPDIF is only 48kHz * 32 bits * 2 channels * 2 for biphase = 6MHz
Any modern FPGA will do 100MHz easy.
So just oversample the signal and decode it like a UART would.

To build a transmitter locked to the receiver would be more difficult.
Alan Nishioka
alann@accom.com

Adam wrote:

> Hello all,
> 
>   Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal?
> I'm trying to build an SPDIF receiver and am wondering if its possible to
> directly connect the input signal(after analog level adjustment) to an FPGA
> and read the level at the 90 and 270 degree phases.  If frames are
> continuously being transmitted when the PLL attempts to lock on, how does it
> know which frequency to use?  It seems if all zeros are being transmitted
> the PLL will lock to half the frequency it should.
> 
> 

Probably not for a Xilinx Virtex II, Spartan III or Virtex II Pro, the 
FPGA specs state that the DCM inputs must have < 1ns period jitter, 
outside which they will lose lock. A true-PLL design may be more 
forgiving, though.

-Jim

Hello all,

  Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal?
I'm trying to build an SPDIF receiver and am wondering if its possible to
directly connect the input signal(after analog level adjustment) to an FPGA
and read the level at the 90 and 270 degree phases.  If frames are
continuously being transmitted when the PLL attempts to lock on, how does it
know which frequency to use?  It seems if all zeros are being transmitted
the PLL will lock to half the frequency it should.