qudhs wrote:

> for all other location, the data is writting correctly. could someone
> point out what could be problem of those "wrong" writing? thank you!

Consider running a simulation with
a walking '1' and walking '0' address.

         -- Mike Treseler

Hi!
does anyone have some experience with the Xilinx EDK OPB_SDRAM
controller?
I am using it to control an 8Mx32 external SDRAM (from Micron). It
appears that not all the writing are done correctly. for some address
space, there is no data or wrong data written to the SDRAM. in fact, the
"wrong" writing happens periodically, as following,
1c, 1d, 1e,1f, 20,21,22,23,28,29,2a,2b (round 1)
5c, 5d, 5e,5f, 60,61,62,63,68,69,6a,6b (round 2, after 0x40 from round
1)
9c, 9d, 9e,9f, a0,a1,a2,a3,a8,a9,aa,ab (round 3, after 0x40 from round
2)
.....

for all other location, the data is writting correctly. could someone
point out what could be problem of those "wrong" writing? thank you!

BRs.
-yang