Top port signals represent wires.
Synthesis requires a process that
uses port and process values to update
process variables and port signals
at each rising_edge(clk).
Such a process might at some point read a port slice:
my_upper_byte_v := my_in_port(7 downto 0);
And perhaps drive a wide port:
my_out_port <= my_uout_byte_v & my_lout_byte_v ;
-- Mike Treseler
Reply by Brad Smallridge●January 14, 20052005-01-14
> Consider declaring each vector part separately.
Thanks Mike,
Hmm. I can do that. What though is happening when I
do a clockless scheduled event,
mem_input( 7 downto 0 ) <= blob_label;
mem_input(15 downto 0) <= blob_volume;
and so on, and with the mem_output going the other way?
It would seem that I'm not creating any hardware, just new
names for the same signals.
Reply by Mike Treseler●January 13, 20052005-01-13
Brad Smallridge wrote:
> I would like to spilt up information on a memory data bus into its
> components. Some text have suggested aliases as a way of doing it. Is it
> the best way?
Consider declaring each vector part separately.
> Modelsim doesn't seem to show the aliases that I define
That's the way it is.
-- Mike Treseler
Reply by Brad Smallridge●January 12, 20052005-01-12
I would like to spilt up information on a memory data bus into its
components. Some text have suggested aliases as a way of doing it. Is it
the best way? Modelsim doesn't seem to show the aliases that I define, or,
more likely, I don't know how to get Modelsim to show aliases. How is that
done?
Brad Smallridge
b r a d @ a i v i s i o n . c o m
415-661-068