Has anybody heard of or done an asynchronous design (delay-intolerant,
isochronic fork, or logical-effort based) on Actel's Axcelerator?

SRAM and Flash FPGAs have a clear bias towards synchronous designs,
but it seems like Actel's antifuse offering isn't as bad for async
design.  Particularly encouraging is the fact that you can create a
stable state element by creating feedback between two combinational
cells -- and Actel even advertises this (in other words, this is not
just unsupported black magic that the manufacturer will disavow).

Also, the structure of the FastConnect and Horizontal Tracks is barely
documented.  Is this a corporate secret?  Is Actel willing to provide
enough information to allow a third party to write a custom routing
tool for the AX architecture?

Thanks,

  - a

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