I am using the same board..and have almost the same problem.
When I use the command below in EDK testAp
Xuint32 FIFO_mReadReg(Xuint32 BaseAddress, unsigned RegOffset
the base address is 0x0000000
shall I use the offset below
#define FIFO_IPIF_RDFIFO_DATA_SPACE_OFFSET (0x00000300
After download the bitstream, I use 'mrd 0x00000300' in xmd, it seem
that nothing is written in the memory..
You can read '1' and '7' at least...but I have nothing........s
sad..
Reply by digi●March 1, 20052005-03-01
Hallo to Al
i use Virtex2pro and edk 6.3i,ise 6.3
I have a problem with the read fifo. I created the fifo with ed
wizard and its a part of IPIF. When you see the vhdl code belove
write in the FIFO(4 Register depth and 32 Bit wide) 4 datas 1,3,5,7
But when i read the registers with the software, i get only datas
and 7. The Datas between get not the fifo
Perhaphs had any the same problem
entity user_logic i
generi
-- ADD USER GENERICS BELOW THIS LINE --------------
--USER generics added her
-- ADD USER GENERICS ABOVE THIS LINE --------------
-- DO NOT EDIT BELOW THIS LINE --------------------
-- Bus protocol parameters, do not add to or delet
C_DWIDTH : integer := 32
C_NUM_CE : integer := 1
C_IP_INTR_NUM : integer := 1
C_RDFIFO_DWIDTH : integer := 32
C_RDFIFO_DEPTH : integer :=
-- DO NOT EDIT ABOVE THIS LINE --------------------
)
por
-- ADD USER PORTS BELOW THIS LINE -----------------
--USER ports added her
switch1 : in std_logic
switch2 : in std_logic
-- ADD USER PORTS ABOVE THIS LINE -----------------
-- DO NOT EDIT BELOW THIS LINE --------------------
-- Bus protocol ports, do not add to or delet
Bus2IP_Clk : in std_logic
Bus2IP_Reset : in std_logic
IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1)
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1)
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1)
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1)
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1)
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1)
IP2Bus_Ack : out std_logic
IP2Bus_Retry : out std_logic
IP2Bus_Error : out std_logic
IP2Bus_ToutSup : out std_logic
IP2RFIFO_WrReq : out std_logic
IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1)
IP2RFIFO_WrMark : out std_logic
IP2RFIFO_WrRelease : out std_logic
IP2RFIFO_WrRestore : out std_logic
RFIFO2IP_WrAck : in std_logic
RFIFO2IP_AlmostFull : in std_logic
RFIFO2IP_Full : in std_logic
RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH)
-- DO NOT EDIT ABOVE THIS LINE --------------------
)
end entity user_logic
-------------------------------------------------------------------------------
-- Architecture sectio
-------------------------------------------------------------------------------
architecture IMP of user_logic i
--USER signal declarations added here, as needed for user logi
---------------------------------------
-- Signals for read/write fifo exampl
---------------------------------------
type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ)
signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE
signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE
signal ip2wfifo_rdreq_cmb : std_logic
signal ip2rfifo_wrreq_cmb : std_logic
signal IP2RFIFO_Data_sig : std_logic_vector(0 t
C_RDFIFO_DWIDTH-1):= (others => '0')
begi
--USER logic implementation added her
---------------------------------------
-- Example code to read/write fif
--
-- Note
-- The example code presented here is to show you one way o
operating o
-- the read/write FIFOs provided by IPIF for you. There's a set o
IPI
-- ports dedicated to FIFOs, beginning with RFIFO2IP_* or IP2RFIFO_
o
-- WFIFO2IP_* or IP2WFIFO_*. Some FIFO ports are only available whe
-- certain FIFO services are present, s.t. vacancy calculation, etc
-- Typically you will need to have a state machine to read data fro
th
-- write FIFO (in IPIF) or write data to the read FIFO (in IPIF)
This cod
-- snippet simply transfer the data from the write FIFO to the rea
FIFO
---------------------------------------
IP2RFIFO_WrMark <= '0'
IP2RFIFO_WrRelease <= '0'
IP2RFIFO_WrRestore <= '0'
--switch : process(switch1
--begi
--if ( switch1 = '0' and switch1'event) the
--go <= '1'
--end if
--if(nogo = '1') the
-- go <= '0'
-- end if
--end process switch
FIFO_CNTL_SM_COMB : process( RFIFO2IP_full, RFIFO2IP_WrAck
fifo_cntl_cs, switch1) i
variable counter : std_logic_vector(0 to 3):= "0000"
constant counter_stop : std_logic_vector(0 to 3):= "1111";
begin
-- set defaults
ip2rfifo_wrreq_cmb <= '0';
fifo_cntl_ns <= fifo_cntl_cs;
case fifo_cntl_cs is
when IDLE =>
if (switch1 = '0') then
counter := (others => '0');
fifo_cntl_ns <= RD_REQ;
end if;
when RD_REQ =>
if ( RFIFO2IP_full = '0') then
counter := counter + 1;
IP2RFIFO_Data_sig(0 to 3) <= counter;
ip2rfifo_wrreq_cmb <= '1';
fifo_cntl_ns <= WR_REQ;
else
ip2rfifo_wrreq_cmb <= '0';
fifo_cntl_ns <= IDLE;
IP2RFIFO_Data_sig <= (others => '0');
end if;
when WR_REQ =>
if ( RFIFO2IP_WrAck = '1' ) then
fifo_cntl_ns <= RD_REQ;
end if;
when others =>
fifo_cntl_ns <= IDLE;
end case;
end process FIFO_CNTL_SM_COMB;
FIFO_CNTL_SM_SEQ : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
IP2RFIFO_WrReq <= '0';
fifo_cntl_cs <= IDLE;
else
IP2RFIFO_WrReq <= ip2rfifo_wrreq_cmb;
fifo_cntl_cs <= fifo_cntl_ns;
end if;
end if;
end process FIFO_CNTL_SM_SEQ;
IP2RFIFO_Data <= IP2RFIFO_Data_sig;
----------------------------------------
-- Example code to drive IP to Bus signals
----------------------------------------
IP2Bus_Data <= (others => '0');
IP2Bus_Ack <= Bus2IP_WrCE(0) or Bus2IP_RdCE(0);
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;