> Hi folks, 
>   I'm trying to get a DDR-SDRAM controller work as an AHB slave.
> According to the transfer timings in the AMBA Spec. Rev. 2, the next 
> transfer can't go on until the slave involved in the previous transfer
> sets the HREADY signal. That means each time a read transfer associated 
> with the DDR is initiated, AHB masters have to wait until the DDR finishes 
> the read burst and puts the read data on the bus, and even another read 
> command involved with the same row as in the current read transfer is not
> allowed. I think that's really a waste in timing, and will lead to a low
> efficiency of the DDR bandwidth.
>   Any solutions?
> regards, 
> Kevin

Euhm, consider doing 'smart' things like prefetch, data buffering,...
I've implemented an AHB bridge to the Altera DDR-SDRAM controller and 
I'm achieving 92% of the bandwith in burst mode. Both read and write. So 
for a DDR333 CAS2.5 and 64 bit DDR I've got 2.4Gbytes/s.

Jan

Hi folks, 
  I'm trying to get a DDR-SDRAM controller work as an AHB slave.
According to the transfer timings in the AMBA Spec. Rev. 2, the next 
transfer can't go on until the slave involved in the previous transfer
sets the HREADY signal. That means each time a read transfer associated 
with the DDR is initiated, AHB masters have to wait until the DDR finishes 
the read burst and puts the read data on the bus, and even another read 
command involved with the same row as in the current read transfer is not
allowed. I think that's really a waste in timing, and will lead to a low
efficiency of the DDR bandwidth.
  Any solutions?
regards, 
Kevin




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