Benjamin,

DesignF/X from http://www.prodacc.com (free trial download) helps
address these kinds of issues; it assists with the import of top-level
HDL, and guides in the tagging of clock pins to specific pins and to
data busses. Once that is done, it also helps you ensure that pins
selected for your data sync are compatible and served by the clock pin
you selected. 

With best wishes,
Manu Pillai

Hi,

I figured out that I have to do it. It works now. Thanks anyway :)

regards,
Benjamin

Hi,

when I use a CLK input-pin in vhdl in my top-level file, is this 
automatically the clk signal of my device? Or do I have to constrain it 
to the correct PIN?

regards,
Benjamin