Duane Clark ha scritto:
>> Hi and thanks for the new files,
>> worked on it again yesterday and now it still doesn't run properly but
>> at least now when I write a 16 bit value the system stalls (before it
>> couldn't write anything from 32 bit to 8 bit: I always got back 0), so
>> it's clear that something as changed (although I don't know if for the
>> better :) ). I'll see if finally I could make it work!
>>
>
> Well, I'll admit to only using with 32 bit values. There may very well
> be problems with other data widths, though I expect a fix would not be
> terribly difficult. That is definitely something that would be a lot
> easier to check in simulation rather than hardware.
Yep, in fact it would be great just to make it work with 32 bit values
for now, so we could have another (big) pool of memory to work with. And
after, if time permits, we could very well try to fix it also for other
data widths with test & simulation in the university lab.
I'll post the MHS of the test-design I made which gives zero with 32
bits value and stalls with 16 bit values. The only modifications I made
to the core in this last test are the elimination of the ext in/out
ports from plb_dimm.vhd (declaring them as signal and tying the in to
0), and after double checking the connections you made within you MHS
and system_top, I just replicated them with the XPS flow. To check if it
was a problem with the flow, I also tried with the projnav flow of
course, but the only difference regarding the dimm core between the
autogenerated system_stub and your system_top is the presence of an
addictional buffer on the DM signals (which aren't on your system_top)
and on the clocks signal different from DDR_CLK0 (buffers are placed as
a standard on all external in/out by EDK when you export the project to
projnav). I'm trying to see if it can work with the XPS flow because it
would be interesting for other people in the lab to be able to use the
core just importing it in EDK...
You can notice psin, psindec and DDR_RST signal tied to zero directly in
the MHS, and I veryfied that this work since exporting the MHS to
projnav gives the correct translation in the system_stub.vhd. Any
suggestion and ideas?
Thank you very much!!!
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = IN
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_DQ_pin = fpga_0_SDRAM_64Mx16_SDRAM_DQ,
VEC = [0:31], DIR = INOUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_BankAddr_pin =
fpga_0_SDRAM_64Mx16_SDRAM_BankAddr, VEC = [0:1], DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_Addr_pin =
fpga_0_SDRAM_64Mx16_SDRAM_Addr, VEC = [0:11], DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_DQM_pin =
fpga_0_SDRAM_64Mx16_SDRAM_DQM, VEC = [0:3], DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_CASn_pin =
fpga_0_SDRAM_64Mx16_SDRAM_CASn, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_RASn_pin =
fpga_0_SDRAM_64Mx16_SDRAM_RASn, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_Clk_pin =
fpga_0_SDRAM_64Mx16_SDRAM_Clk, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_WEn_pin =
fpga_0_SDRAM_64Mx16_SDRAM_WEn, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_SDRAM_CSn_pin =
fpga_0_SDRAM_64Mx16_SDRAM_CSn, DIR = OUT
PORT fpga_0_SDRAM_64Mx16_emc_disable_flash_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_SDRAM_64Mx16_emc_disable_sram_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_SDRAM_64Mx16_emc_disable_buffer_pin = net_vcc, DIR = OUTPUT
PORT fpga_0_SDRAM_64Mx16_emc_disable_sysace_pin = net_vcc, DIR = OUT
PORT sys_clk_pin = dcm_clk_s, DIR = IN
PORT sys_rst_pin = sys_rst_s, DIR = IN
PORT DDR_AD = plb_dimm_0_DDR_Addr, DIR = OUT, EDGE = RISING, VEC = [0:12]
PORT DDR_BA = plb_dimm_0_DDR_BankAddr, DIR = OUT, EDGE = RISING, VEC =
[0:1]
PORT DDR_CASB = plb_dimm_0_DDR_CASn, EDGE = RISING, DIR = OUT
PORT DDR_CKE = plb_dimm_0_DDR_CKE, DIR = OUT, EDGE = RISING, VEC = [0:1]
PORT DDR_CSB = plb_dimm_0_DDR_CSn, DIR = OUT, EDGE = RISING, VEC = [0:1]
PORT DDR_DM = plb_dimm_0_DDR_DM, DIR = OUT, EDGE = RISING, VEC = [0:7]
PORT DDR_DQ = plb_dimm_0_DDR_DQ, DIR = INOUT, EDGE = RISING, VEC = [0:63]
PORT DDR_DQS = plb_dimm_0_DDR_DQS, DIR = INOUT, EDGE = RISING, VEC = [0:7]
PORT DDR_RASB = plb_dimm_0_DDR_RASn, EDGE = RISING, DIR = OUT
PORT DDR_WEB = plb_dimm_0_DDR_WEn, EDGE = RISING, DIR = OUT
PORT DDR_CLKB_0 = plb_dimm_0_DDR_Clkn_0, EDGE = RISING, DIR = OUT
PORT DDR_CLKB_1 = plb_dimm_0_DDR_Clkn_1, EDGE = RISING, DIR = OUT
PORT DDR_CLK_0 = plb_dimm_0_DDR_Clk_0, EDGE = RISING, DIR = INOUT
PORT DDR_CLK_1 = plb_dimm_0_DDR_Clk_1, EDGE = RISING, DIR = OUT
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE DPLB = plb
BUS_INTERFACE IPLB = plb
BUS_INTERFACE JTAGPPC = jtagppc_0_0
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = cpmc405clock
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_ADDR_RNG = 1
PARAMETER C_RNG0_BASEADDR = 0x81000000
PARAMETER C_RNG0_HIGHADDR = 0x8100ffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
PORT PLB_Clk = sys_clk_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 19200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x81000000
PARAMETER C_HIGHADDR = 0x8100ffff
BUS_INTERFACE SOPB = opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN plb_sdram
PARAMETER INSTANCE = SDRAM_64Mx16
PARAMETER HW_VER = 1.00.e
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
PARAMETER C_PLB_CLK_PERIOD_PS = 10000
PARAMETER C_SDRAM_TMRD = 2
PARAMETER C_SDRAM_TCCD = 1
PARAMETER C_SDRAM_TRAS = 50000
PARAMETER C_SDRAM_TRC = 100000
PARAMETER C_SDRAM_TRFC = 100000
PARAMETER C_SDRAM_TRCD = 20000
PARAMETER C_SDRAM_TRRD = 20000
PARAMETER C_SDRAM_TRP = 20000
PARAMETER C_SDRAM_TREF = 64
PARAMETER C_SDRAM_CAS_LAT = 2
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_SDRAM_AWIDTH = 12
PARAMETER C_SDRAM_DWIDTH = 32
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x01ffffff
BUS_INTERFACE SPLB = plb
PORT PLB_Clk = sys_clk_s
PORT SDRAM_CLK_in = sys_clk_s
PORT SDRAM_DQ = fpga_0_SDRAM_64Mx16_SDRAM_DQ
PORT SDRAM_Addr = fpga_0_SDRAM_64Mx16_SDRAM_Addr
PORT SDRAM_DQM = fpga_0_SDRAM_64Mx16_SDRAM_DQM
PORT SDRAM_WEn = fpga_0_SDRAM_64Mx16_SDRAM_WEn
PORT SDRAM_CSn = fpga_0_SDRAM_64Mx16_SDRAM_CSn
PORT SDRAM_CASn = fpga_0_SDRAM_64Mx16_SDRAM_CASn
PORT SDRAM_RASn = fpga_0_SDRAM_64Mx16_SDRAM_RASn
PORT SDRAM_Clk = fpga_0_SDRAM_64Mx16_SDRAM_Clk
PORT SDRAM_BankAddr = fpga_0_SDRAM_64Mx16_SDRAM_BankAddr
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
BUS_INTERFACE SPLB = plb
PORT PLB_Clk = sys_clk_s
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN plb_dimm
PARAMETER INSTANCE = plb_dimm_0
PARAMETER HW_VER = 1.11.a
PARAMETER C_MEM0_BASEADDR = 0x40000000
PARAMETER C_MEM0_HIGHADDR = 0x47ffffff
PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 0
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CLK_PAIRS = 2
PARAMETER C_FAMILY = virtex2
PARAMETER C_INCLUDE_ECC_SUPPORT = 0
PARAMETER C_DDR_TMRD = 2
PARAMETER C_DDR_TWR = 15000
PARAMETER C_DDR_TWTR = 1
PARAMETER C_DDR_TRAS = 40000
PARAMETER C_DDR_TRC = 65000
PARAMETER C_DDR_TRFC = 75000
PARAMETER C_DDR_TRCD = 20000
PARAMETER C_DDR_TRRD = 15000
PARAMETER C_DDR_TREFC = 70000000
PARAMETER C_DDR_TREFI = 7800000
PARAMETER C_DDR_TRP = 20000
PARAMETER C_DDR_CAS_LAT = 3
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_DDR_AWIDTH = 12
PARAMETER C_DDR_COL_AWIDTH = 9
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_PLB_CLK_PERIOD_PS = 10000
BUS_INTERFACE SPLB = plb
PORT DDR_Rst = 0b0
PORT Clk90_in = plb_dimm_0_Clk90_in
PORT DDR_Addr = plb_dimm_0_DDR_Addr
PORT DDR_BankAddr = plb_dimm_0_DDR_BankAddr
PORT DDR_CASn = plb_dimm_0_DDR_CASn
PORT DDR_CKE = plb_dimm_0_DDR_CKE
PORT DDR_Clk90_in = plb_dimm_0_DDR_Clk90_in
PORT DDR_Clkn_0 = plb_dimm_0_DDR_Clkn_0
PORT DDR_Clkn_1 = plb_dimm_0_DDR_Clkn_1
PORT DDR_Clk_0 = plb_dimm_0_DDR_Clk_0
PORT DDR_Clk_1 = plb_dimm_0_DDR_Clk_1
PORT DDR_Clk_fb = plb_dimm_0_DDR_Clk_fb
PORT DDR_CSn = plb_dimm_0_DDR_CSn
PORT DDR_DCM_Locked = plb_dimm_0_DDR_DCM_Locked
PORT DDR_DCM_Reset = plb_dimm_0_DDR_DCM_Reset
PORT DDR_DM = plb_dimm_0_DDR_DM
PORT DDR_DQ = plb_dimm_0_DDR_DQ
PORT DDR_DQS = plb_dimm_0_DDR_DQS
PORT DDR_RASn = plb_dimm_0_DDR_RASn
PORT DDR_WEn = plb_dimm_0_DDR_WEn
PORT PLB_Clk = sys_clk_s
PORT PLB_DCM_Locked = dcm_0_lock
END
BEGIN ddr_clocks
PARAMETER INSTANCE = ddr_clocks_0
PARAMETER HW_VER = 1.00.a
PORT ref_clk = dcm_clk_s
PORT ddr_dcm_rst = plb_dimm_0_DDR_DCM_Reset
PORT sys_rst_n = net_vcc
PORT plb_opb_clk = sys_clk_s
PORT cpmc405clock = cpmc405clock
PORT clk90_in = plb_dimm_0_Clk90_in
PORT ddr_clk_fb = plb_dimm_0_DDR_Clk_fb
PORT ddr_clk90_in = plb_dimm_0_DDR_Clk90_in
PORT ddr_clk_locked = plb_dimm_0_DDR_DCM_Locked
PORT plb_opb_locked = dcm_0_lock
PORT psen = 0b0
PORT psincdec = 0b0
END