Dan,

At the top level, just instantiate the 'p' signal from your pair.  Next
assign this to pin 123 or 124, whichever is the 'p' I/O.  The Quartus
software will take car of creating the 'n' signal, and it will place it
next to 'p'.  In your design, do you plan on using this a normal I/O or
a serialized I/O.  If it's normal (i.e. SDR or DDR), you don't have to
do anything special.  Just use it like any other port.  If is is
serialized, you must instantiate Altera's SERDES core.  The output of
the core will have a std_logic_vector that you can use.

John M

I have 2 signals that come from an lvds transmitter sources: lvds1p,
lvds1n.
I use an cyclone EP1C6. I want to put these signals on pins 124 and
123.
    how can i make this and how a can use after that this signal in my
design
 (transmitter -> lvds1p,lvds1n ->fpga:receive these signals -> how can
i group then in signal lvds and the use this final signal ????)
  I use Quartus4.1


 Thanks