naveen wrote:

> Hi,
>    But if the host frequency is different from pci frequency we need
> to keep asynchronous fifo, i guess. Am i true? In that case do we need
> totally 4 fifos?

Yes, asynchronous clocks complicate the design substantially,
especially in view of metastability issues.

But two buffers (one upstream and one downstream) should be 
sufficient. The only thing you have to take care for is to 
avoid deadlock-conditions during simultaneous access-attempts
from both sides.

> Also, can i get any document of implementation for host-pci bridge on
> net? I searched but unable to find out.

I don't know whether there is a documentation as such available.
However, a host bridge is not some general thing as it's requirements
depend heavily on the host bus. Consider to have a look inside the 
PCI-to-PCI bridge spec. There you might find important hints for 
general bridge design. 

> In case of configuration transactions in host-pci bridge how will be
> the flow?

Actually, there is no special requirement. The PCI spec (2.1s) specifies
two modes for "normal" PC systems: A mode with a few control registers 
(easy to implement) and a mode with IO-mapping (a little bit more
difficult). But generally it is left open how one implements a 
mechanism for generating those transactions.

Regards,
Mario

Hi,
   But if the host frequency is different from pci frequency we need
to keep asynchronous fifo, i guess. Am i true? In that case do we need
totally 4 fifos?
Also, can i get any document of implementation for host-pci bridge on
net? I searched but unable to find out.
In case of configuration transactions in host-pci bridge how will be
the flow?
naveen


Mario Trams <Mario.Trams@informatik.tu-chemnitz.de> wrote in message news:<blgnka$jie$1@anderson.hrz.tu-chemnitz.de>...
> naveen wrote:
> 
> > Hi group,
> >           I had a small clarification on Host-PCI Bridge. For Host-PCI
> > bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge
> 
> The PCI-to-PCI bridge spec is intended just for what it says. 
> It does not cover host-bridge issues. 
> That is at least true for the PCI-to-PCI bridge spec I've at hand here.
> Nevertheless, it cannot be a mistake to read this spec as well when
> designing other bridges.
> 
> > specs. are needed? Also in case of a Host-PCI Bridge, can we have
> > Memory Read line, Memory Read Multiple, Memory write and invalidate
> 
> Of course. Why not?
> 
> > commands executed? If we need to implement them do we need larger fifo
> > inside the bridge? Minimum of how many fifos do we need in a Host to
> > PCI Bridge Design?
> 
> It depends mainly on your host bus. If you don't want to support 
> delayed transaction completion (especially for reads but also for 
> writes) you do not need FiFos (or better say buffers) at all. 
> When there's some data not available, you could easily deassert 
> TRDY# until the data becomes available. 
> Btw., a PCI-to-PCI bridge is also not required to implement any 
> data buffers.
>  
> Of course, that is not the best idea in view of PCI bus efficiency.
> But finally it depends on the final application and how much time 
> you want invest to develop your host bridge (and how much space you
> have available in your FPGA ;-).
> 
> Regards,
> Mario

naveen wrote:

> Hi group,
>           I had a small clarification on Host-PCI Bridge. For Host-PCI
> bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge

The PCI-to-PCI bridge spec is intended just for what it says. 
It does not cover host-bridge issues. 
That is at least true for the PCI-to-PCI bridge spec I've at hand here.
Nevertheless, it cannot be a mistake to read this spec as well when
designing other bridges.

> specs. are needed? Also in case of a Host-PCI Bridge, can we have
> Memory Read line, Memory Read Multiple, Memory write and invalidate

Of course. Why not?

> commands executed? If we need to implement them do we need larger fifo
> inside the bridge? Minimum of how many fifos do we need in a Host to
> PCI Bridge Design?

It depends mainly on your host bus. If you don't want to support 
delayed transaction completion (especially for reads but also for 
writes) you do not need FiFos (or better say buffers) at all. 
When there's some data not available, you could easily deassert 
TRDY# until the data becomes available. 
Btw., a PCI-to-PCI bridge is also not required to implement any 
data buffers.
 
Of course, that is not the best idea in view of PCI bus efficiency.
But finally it depends on the final application and how much time 
you want invest to develop your host bridge (and how much space you
have available in your FPGA ;-).

Regards,
Mario 
  

Hi group,
          I had a small clarification on Host-PCI Bridge. For Host-PCI
bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge
specs. are needed? Also in case of a Host-PCI Bridge, can we have
Memory Read line, Memory Read Multiple, Memory write and invalidate
commands executed? If we need to implement them do we need larger fifo
inside the bridge? Minimum of how many fifos do we need in a Host to
PCI Bridge Design?
Thanks
Naveen