> The Spartan-3 consumes many milliwatts...

As far as the Spartan-3 power requirements, that is fine as I am
designing with this part already. The part cited in the xilinx tech
notes suggested 24 mA LVTTL output buffer and a comparator. I was
hoping to devise the external circuitry that had requirements in the
nanoWatt range. (See also other post for description of nanoWatt).
Thanks,
-Herbie

> I am looking at an application that will provide an analog input
signal
> in the 125 to 500 KHz frequency range, and wanted to convert it to a
> digital signal that would be processed by a Spartan 3 FPGA.

You're probably much better off just buying an ADC capable of sampling
at whatever frequency you want, and connecting it to your FPGA through
the converter's interface.  You'll get much better performance and you
won't have to do tricks to make the FPGA do something a standalone part
will do much better and for less money.

-a

nanoWatt is a term that was used by microchip, and has the following
specification:

Low-Power Features:
=B7 Standby Current:
- 1 nA @ 2.0V, typical
=B7 Operating Current:
- 8.5=B5A @ 32 kHz, 2.0V, typical
- 100=B5A @ 1 MHz, 2.0V, typical
=B7 Watchdog Timer Current:
- 1=B5A @ 2.0V, typical

See also http://ww1.microchip.com/downloads/en/DeviceDoc/41200B.pdf

Thanks,
-Herbie

The app notes are not limited to Virtex. You can use the same ideas on
Spartan-3.
What do you mean by nano-watt?
The Spartan-3 consumes many milliwatts...
Peter Alfke, Xilinx Applications

Greetings,
I am looking at an application that will provide an analog input signal
in the 125 to 500 KHz frequency range, and wanted to convert it to a
digital signal that would be processed by a Spartan 3 FPGA. I found two
xilinx app notes that address issues related these areas (but based on
Virtex FPGA):

http://www.xilinx.com/bvdocs/appnotes/xapp155.pdf (Virtex ADC)
http://www.xilinx.com/bvdocs/appnotes/xapp154.pdf (Virtex Delta-Sigma
DAC)

My other hardware requirements are low power (nanoWatt). I am wondering
if you can help me in the following areas:

1. Is it possible to achieve these goals given the requirements
(125-500 KHz input signal, low power consumption, Spartan 3)? Note: The
input frequency cycles at 125 KHz. Thus my thought is if I can devise a
circuit that perhaps operates at 500 KHz, that is sufficient tolerance
to assume that within the 500 KHz range the 125 KHz can be assumed to
be slowly changing or linear.

2. My thought is that it is possible to implement these using Spartan
3, but the cited links were to Virtex architecture. What concerns come
to mind for the transition?

3. Reasonable expectations about the resolution/accuracy of such
sampled analog signals?

(a) For example, I am only able to discretize the analog input signal
into an 8 or 10 bit resolution (meaning that 2^8 is 256 output values
for the vertical axis, thus it is an expectation for the measure of
round-off errors).

(b) Eventhough the Spartan 3 can run at 50 MHz, the ADC would only be
able to sample slowly changing signals (<20 KHz).

4. Reference to understanding basics about ADC (e.g books, web sites,
etc)?

Thanks,
-Herbie